Publication News

PUBLICATION NEWS
Special Issue on Circuits and Computing Architectures in the Emerging Area of Nanotechnology The November 2007 issue of IEEE Transactions on Circuits and Systems, Part-I will be a special issue on circuits and computing architectures in the emerging area of Nanotechnology. This, of course, is a small, but hopefully representative, slice of a large emerging area of research. The special issue is guest edited by Cliff Lau from Institute of Defense Analysis (IDA), Alex Orailoglu from UC San Diego and Kaushik Roy from Purdue. Thanks to Cliff, who led the team, Alex and Kaushik for putting it together. Please read the "Note from EiC" and the "Guest Editorial" when the issue appears in print (or in IEEE Xplore) to appreciate some historical background on how the special issue came about. Actually, there is more, that space does not allow us to write. We hope you find the issue timely, relevant and entertaining. A list of abstracts follow.

Title: On Circuit Theories for Single-Electron Tunneling Devices
Authors: Jaap Hoekstra Abstract - In this paper, various approaches to modeling tunneling and Coulomb blockade in circuits that include metallic single-electron tunneling devices are reviewed, and tested for their usefulness for designing nanoelectronic circuits. The approaches differ in the way they incorporate the quantization of charge into a circuit theory. First, the quantum phenomena important for single-electron tunneling devices are presented. Second, two energy based theories are discussed, together often called orthodox theory of single electronics. The focus is on the transition from a device description to a circuit theory. In the orthodox theory the quantization of charge leads to the quantization of the continuous spectrum of energy states associated with the capacitance of small metal islands. In the third section the, on direct-tunneling based, impulse circuit model is discussed that translates the quantization of charge into the quantization of current and of time during a tunnel event. The conclusion is that the orthodox theory of single electronics poses severe problems when used as a circuit theory; the impulse circuit model provides a better starting point.
Title: Modeling of the Electrical Conductivity of DNA Authors: Vedrana Hodzic, Vildana Hodzic, Robert W. Newcomb Abstract - We have developed a PSpice model of the electrical behavior of DNA molecules for use in nanoelectronic circuit design. To describe the relationship between the current through DNA and the applied voltage we used published results of the direct measurements of electrical conduction through DNA molecules. The experimental dc current-voltage (I-V) curves show a nonlinear conduction mechanism as well as the existence of a temperature dependent semiconductive voltage gap. A weighted least-squares polynomial fit to the experimental data at one temperature, with fitted temperature dependent polynomial coefficient of the linear term, was used as a mathematical model of electrical behavior of DNA. An equivalent electrical circuit was created in PSpice in which DNA was modeled as a voltage-controlled current source described by the mathematical model that includes temperature dependence, GPOLY(T) . PSpice simulations with this model generated current-voltage-curves at other temperatures that were in excellent agreement with the corresponding experimental data (average deviation < 5%). This is important because having models of DNA molecules in the form of equivalent electronic circuits would be useful in the design of nanoelectronic circuits and devices. Title: CNTFET Modeling and Reconfigurable Logic Circuit Design Authors: Ian O'Connor, Junchen Liu, Fridiric Gaffiot, Fabien Prigaldiny, Christophe Lallement, Cristell Maneux, Johnny Goguet, Sebastien Frigonhse, Thomas Zimmer, Lorena Anghel, Trinh Dang, Rigis Leveugle Abstract - This paper examines aspects of design technology required to explore advanced logic circuit design using CNTFET devices. An overview of current types of CNTFETs is given and highlights the salient characteristics of each. Compact modeling issues are addressed and new models are proposed implementing (i) a physics-based calculation of energy conduction sub-band minima to allow a realistic analysis of the impact of CNT helicity and radius on the dc characteristics and (ii) descriptions of ambipolar behavior in Schottky-Barrier CNTFETs and ambivalence in double-gate CNTFETs. Using the available models, the influence of the parameters on the device characteristics were simulated and analyzed. The exploitation of properties specific to CNTFETs to build functions inaccessible to MOSFETs is also described, particularly with respect to the use of double-gate CNTFETs in fine-grain reconfigurable logic. Title: A Programmable Majority Logic Array using Molecular Scale Electronics Authors: Garrett S. Rose and Mircea R. Stan Abstract - In recent years many advances have been made in the development of molecular scale electronics which have inspired interest in using the devices thereof for memory and logic. This paper describes the design of a logic architecture using a particular class of molecular devices. Specifically, it is shown that the feature of hysteretic switching common to many molecular devices can be utilized to build programmable arrays. Also utilized in the designs presented here are molecular devices which exhibit negative differential resistance (NDR), a property useful for providing signal restoration at the nanoscale. This work begins by describing the potential for both programmability and NDR in molecular scale electronics. These ideas are then brought together in the design of a programmable logic array based on majority logic. Title: Carbon Nanotube Electronics: Design of High Performance and Low Power Digital Circuits Authors: Arijit Raychowdhury and Kaushik Roy Abstract - Scaling of Silicon transistors continue in the sub 100nm regime amidst severe roadblocks. Increased short channel effects, rising leakage currents, severe process parameter variations are only a few of the overwhelming challenges that the device and circuit designers are faced with. In an attempt to alleviate the problems associated with the scaling of silicon transistors, researchers have began a quest for novel alternate materials in a post-Si nanoelectronics era. Of the different materials investigated so far, carbon nanotubes with their superior transport properties, excellent thermal conductivities and high current handling capacities have proved to be a potential heir to Si. This paper reviews the promise of carbon nanotube field effect transistors (CNFETs) as future devices for high performance as well as low power electronics. Title: A Defect Tolerance Scheme for Nanotechnology Circuits Authors: Ahmad Al-Yamani, S. Ramsundar, Dhiraj K. Pradhan Abstract - Lithography based IC fabrication is rapidly approaching its limit in terms of feature size. The current alternative is nanotechnology based fabrication, which relies on self-assembly of nanotubes or nanowires. Such a process is subject to a high defect rate, which can be tolerated using carefully crafted defect tolerance techniques. This paper presents an algorithm for reconfiguration-based defect tolerance in nanotechnology switches. The algorithm offers an average switch density improvement of 50% to 100% to most recently published techniques. The algorithm is also consistent in improving the yield through minimizing false rejects as the results show over a large sample. The improvement percentage varies depending on the manufactured switch size and the desired defect-free size with the improvement in efficiency directly proportional to the size of the switch. Title: Defect Tolerance Based on Coding and Series-Replication in Transistor-Logic Demultiplexer Circuits Authors: Warren Robinett, Philip J. Kuekes, and R. Stanley Williams Abstract - We present a family of defect-tolerant, transistor-logic demultiplexer circuits that can defend against both stuck-ON (short defect) and stuck-OFF (open defect) transistors. Short defects are handled by having two or more transistors in series in the circuit, controlled by the same signal. Open defects are handled by having two or more parallel branches in the circuit, controlled by the same signals, or more efficiently, by using a method based on error-correcting codes. These circuits are evaluated, in comparison with an unprotected demultiplexer circuit, by (1) modeling each circuit's ability to tolerate defects and (2) calculating the cost of the defect tolerance as each circuit's redundancy factor R, which is the relative number of transistors required by the circuit. The defect-tolerance model takes the form of a probability function giving the failure rate of the entire demultiplexer circuit as a function of the defect rates of its component transistors, for both defect types. Title: Fault-Tolerant Nanoscale Processors on Semiconductor Nanowire Grids Authors: Csaba Andras Moritz, Teng Wang, Pritish Narayanan, Michael Leuchtenburg, Yao Guo, Catherine Dezan, and Mahmoud Bennaser Abstract - Nanoscale processor designs pose new challenges not encountered in the world of conventional CMOS designs and manufacturing. Nanoscale devices based on crossed semiconductor nanowires (NWs) have promising characteristics in addition to providing great density advantage over conventional CMOS devices. This density advantage could, however, be easily lost when assembled into nanoscale systems and especially after techniques dealing with high defect rates and manufacturing related layout/doping constraints are incorporated. Most conventional defect/fault-tolerance techniques are not suitable in nanoscale designs because they are designed for very small defect rates and assume arbitrary layouts for required circuits. Reconfigurable approaches face fundamental challenges including a complex interface between the micro and nano components required for programming. In this paper, we present our work on adding fault-tolerance to all components of a processor implemented on a 2-D semiconductor nanowire (NW) fabric called NASICs. We combine and explore structural redundancy, built-in nanoscale error correcting circuitry, and system-level redundancy techniques and adapt the techniques to the NASIC fabric. Faulty signals caused by defects and other error sources are masked on-the-fly at various levels of granularity. Faults can be masked at up to 15% rates, while maintaining a 7X density advantage compared to an equivalent CMOS processor at projected 18nm technology. Detailed analysis of yield, density, and area tradeoffs is provided for different error sources and fault distributions. Title: An Information Theoretical Framework for Analysis and Design of Nano-Scale Fault-Tolerant Memories Based on Low-Density Parity-Check Codes Authors: Bane Vasic and Shashi Kiran Chilappagari Abstract - In this paper we develop a theoretical framework for the analysis and design of fault-tolerant memory architectures. Our approach is a modification of the method developed by Taylor and refined by Kuznetsov. Taylor and Kuznetsov (TK) showed that memory systems have nonzero computational (storage) capacity, i.e. the redundancy necessary to ensure reliability grows asymptotically linearly with the memory size. The restoration phase in the TK method is based on low-density parity-check (LDPC) codes which can be decoded using low complexity decoders. The equivalence of the restoration phase in the TK method and faulty Gallager-B algorithm enabled us to establish a theoretical framework for solving problems in reliable storage on unreliable media using the large body of knowledge in codes on graphs and iterative decoding gained in the past decade. Title: Reliability analysis of large circuits using scalable techniques and tools Authors: Debayan Bhaduri, Sandeep Shukla, Paul Graham, Maya Gokhale Abstract - The rapid development of CMOS and non-CMOS nanotechnologies has opened up new possibilities and introduced new challenges for circuit design. One of the main challenges is in designing reliable circuits from defective nanoscale devices. Hence, there is a need to develop methodologies to accurately evaluate circuit reliability. In recent years, a number of reliability evaluation methodologies based on probabilistic model checking, probabilistic transition matrices, probabilistic gate models, etc., have been proposed. Scalability has been a concern in the applicability of these methodologies to the reliability analysis of large circuits. In this paper, we develop a general, scalable technique for these reliability evaluation methodologies. Specifically, an algorithm is developed for the model checkingbased methodology and implemented in a tool called SETRA (Scalable, Extensible Tool for Reliability Analysis). SETRA integrates the scalable model checking-based algorithm into the conventional CAD circuit design flow. The paper also discusses ways to modify the scalable algorithm for the other reliability estimation methodologies and plug them into SETRA's extensible framework. Our preliminary experiments show how SETRA can be used effectively to evaluate and compare the robustness of different circuit designs. Title: Nanocell devices and architecture for configurable computing with molecular electronics Authors: Jonas Skvldberg, Gvran Wendin, Carl Vnnheim Abstract - We develop a method to configure a 3-dimensional non-linear nanoparticle-molecule network to performing ten out of twelve possible combinations of two 2-bit logic gates with shared inputs. The logic gates are based on a simple circuit with adjustable linear and fixed negative differential resistance (NDR) elements. A bistable latch for signal restoration is an integral part of this target circuit. The simulations show that conductive patterns can be formed by applying voltages on the I/O pins of the nanocell. They also show that one-link gaps (short highly resistive links) can be created within the conductive channels. Furthermore, we discuss methods for introducing NDR molecules in these gaps, a crucial element of the target circuit. The structures resulting from the simulations are put in an architectural context, in which complex functions can be realized from the individual nanocell logic gates. Title: 3D Nanoarchitectures with carbon nanotube mechanical switches for future on-chip network beyond CMOS architecture Authors: Shinobu Fujita, Kumiko Nomura, Keiko Abe and Thomas H. Lee Abstract - We have proposed 3D Nanoarchitectures with carbon nanotube based nano-electro-mechanical (CNT-NEMS) switch with a floating gate. It is shown that logic based on them has a potential to overcome CMOS using process technology less than 45 nm. Furthermore, CNT-NEMS based 3D circuits realize extremely high bandwidth over 10 Peta-bite/s cm2 with very low latency less than several 10 ps. The most effective applications is 3D on-chip crossbar bus and future on-chip network, which dominates performance of future micro-chips. The performance of 3D on-chip crossbar based on CNT-NEMS is also compared with that on CNT-transistors. Title: Hybridization of CMOS with CNT-Based Nano Electromechanical Switch for Low Leakage and Robust Circuit Design Using Nanoscaled CMOS Devices Authors: Rajat Subhra Chakraborty, Seetharam Narasimhan, and Swarup Bhunia Abstract - Exponential increase in leakage power has emerged as a major barrier to technology scaling. Existing circuit techniques for leakage reduction either suffer from reduced effectiveness at nanometer technologies (such as dual Vth assignment, adaptive body biasing etc.) or affect performance and gate-oxide reliability (such as supply gating, MTCMOS etc.). In this paper, we propose the application of a specific carbon nanotube based nano electro-mechanical switch as the leakage control structure in logic and memory circuits as well as non-volatile data retention mechanism during standby mode. In case of memory circuits, we demonstrate that the proposed hybridization can be employed to reduce both cell leakage and bitline leakage, thereby improving its read noise margin as well. Due to the unique electro-mechanical properties of carbon nanotubes, these switches have high current carrying capacity, extremely low leakage current, and low operating voltages. Moreover, they can act as nonvolatile memory elements, which can be exploited for data retention of important registers and latches during power down. Simulation results for a set of ISCAS benchmark circuits show that we can obtain several orders of magnitude improvement in leakage saving in logic circuits at iso-performance compared to existing MTCMOS technique for leakage reduction. In memory circuits, simulations show ~19X reduction in standby leakage power and ~55X reduction in bitline leakage compared with the best existing techniques. Title: 3D nFPGA: A Reconfigurable Architecture for 3D CMOS/Nanomaterial Hybrid Digital Circuits Authors: Chen Dong, Deming Chen, Sansiri Haruehanroengra and Wei Wang Abstract - In this paper, we introduce a novel reconfigurable architecture, named 3D nFPGA, which utilizes 3D integration techniques and new nanoscale materials synergistically. The proposed architecture is based on CMOS-nano hybrid techniques that incorporate nanomaterials such as carbon nanotube bundles and nanowire crossbars into CMOS fabrication process. This architecture also has built-in features for fault tolerance and heat alleviation. Using unique features of FPGAs and a novel 3D stacking method enabled by the application of nanomaterials, 3D nFPGA obtains a 4X footprint reduction comparing to the traditional CMOS-based 2D FPGAs. With a customized design automation flow, we evaluate the performance and power of 3D nFPGA driven by the 20 largest MCNC benchmarks. Results demonstrate that 3D nFPGA is able to provide a performance gain of 2.6X with a small power overhead comparing to the traditional 2D FPGA architecture. Title: Cortical Models onto CMOL and CMOS - Architectures and Performance/price Authors: Changjian Gao and Dan Hammerstrom Abstract - Here we introduce a highly simplified model of the neocortex based on spiking neurons, and then investigate various mappings of this model to the CMOL CrossNet nanogrid nanoarchitecture. The performance/price is estimated for several architectural configurations both with and without nano-scale circuits. In this analysis we explore the time multiplexing of computational hardware for a pulse based variation of the model. Our analysis demonstrates that the mixed-signal CMOL implementation has the best performance/price in both non-spiking and spiking neural models. However, these circuits also have serious power density issues when interfacing the nanowire crossbars to analog CMOS circuits. Although the results presented here are based on biologically based computation, the use of pulse based data representation for nano-scale circuits has much potential as a general architectural technique for a range of nano-circuit implementation. Title: A Novel Hybrid Phase-locked-loop Frequency Synthesizer Using Single Electron Devices and CMOS Transistors Authors: Wancheng Zhang andn Nan-jian Wu Abstract - This paper proposes a novel phase-locked-loop (PLL) frequency synthesizer using single-electron devices (SEDs) and metal-oxide-semiconductor (MOS) field-effect-transistors. The PLL frequency synthesizer mainly consists of a single electron transistor (SET)/MOS hybrid VCO circuit, a single-electron turnstile/MOS hybrid phase-frequency-detector (PFD) circuit and a single-electron turnstile/MOS hybrid frequency-divider. The phase-frequency detection and frequency-division functions are realized by manipulating the single electrons. We propose a SPICE model to describe the behavior of the MOSFET-based single-electron turnstile. We simulate the performance of the PLL block circuits and the whole PLL synthesizer. Simulation results indicated that the circuit can well perform the operation of the PLL frequency synthesizer at room temperature. The PLL synthesizer is very compact. The total number of the transistors is less than 50. The power dissipation of the proposed PLL circuit is less than 3uW. We discuss the effect of fabrication tolerance, the effect of background charge and the SE transfer accuracy on the performance of the PLL circuit. A technique to compensate parameter dispersions of SEDs is proposed. Title: Designs for Ultra-Tiny, Special-Purpose Nanoelectronic Circuits Authors: Shamik Das, Alexander J. Gates, Hassen A. Abdu, Garrett S. Rose, Carl A. Picconatto, and James C. Ellenbogen Abstract - Designs and simulation results are given for two small, special-purpose nanoelectronic circuits. The area of special-purpose nanoelectronics has not been given much consideration previously, though much effort has been devoted to the development of general-purpose nanoelectronic systems, i.e., nanocomputers. This paper demonstrates via simulation that the nanodevices and nanofabrication techniques developed recently for general-purpose nanocomputers also might be applied with substantial benefit to develop less complex nanocircuits targeted at specific applications. Nanocircuits considered here are a digital controller for the leg motion on an autonomous millimeter-scale robot and an analog nanocircuit for amplification of signals in a tiny optoelectronic sensor or receiver. Simulations of both nanocircuit designs show significant improvement over microelectronic designs in metrics such as footprint area and power consumption. These improvements are obtained from designs employing nanodevices and nanofabrication techniques that already have been demonstrated experimentally. Thus, the results presented here suggest that such improvements might be realized in the near term for important, special-purpose applications. Title: The Potential of FinFETs for Analog and RF Circuit Applications Authors: Piet Wambacq, Bob Verbruggen, Karen Scheir, Jonathan Borremans, Morin Dehan, Dimitri Linten, Vincent De Heyn, Geert Van der Plas, Abdelkarim Mercha, Bertrand Parvais, Cedric Gustin, Vaidy Subramanian, Nadine Collaert, Malgorzata Jurczak, Stefaan Decoutere Abstract - CMOS downscaling in the nanoscale era will necessitate drastic changes to the planar bulk CMOS transistor to keep pace with the required speed increase while at the same time maintaining acceptable performance in terms of leakage, variability and analog parameters such as gain, noise and linearity. For the gate electrode and the gate dielectric, which classically uses polysilicon and SiO2 with some amount of nitridation, new materials might be needed. Also, a new transistor architecture might be required that deviates from the planar structure. Thanks to their inherent suppression of short channel effects, reduced drain-induced barrier lowering and good scalability, multi-gate devices such as FinFETs are considered as possible candidates for device scaling at the end of ITRS Roadmap. As such they form a first step between a planar architecture and a silicon nanowire. In this paper we demonstrate with functional prototypes of analog and RF circuits that the combination of a new gate stack with a FinFET transistor architecture outperforms comparable circuit realizations in planar bulk CMOS for low to moderate speed. Further, the FinFETs exhibit less leakage and show less intra-die variability than their planar bulk counterpart. In the microwave and millimeter-wave frequency region, planar bulk CMOS is still superior. The main challenge for FinFET performance in the coming years is the improvement of the maximum cutoff frequency, which is nowadays limited to 100 GHz. Title: Quantum Circuit Design and Analysis for Database Search Applications Authors: Yi-Ling Ju, I-Ming Tsai, and Sy-Yen Kuo Abstract - In this paper, we show how quantum Boolean circuits can be used to implement the oracle and the inversion about-average function in Grover's search algorithm. We give detailed circuit design including how to recover the auxiliary qubits to improve the reliability of the quantum system. We first present the circuit design principle using the satisfiability (SAT) problem as an example. Then, based on this principle, we show the quantum circuits for two different kinds of applications. The first one is searching a phone book. Although this is a typical example of Grover's algorithm, we show that it is impractical as a real-world application. As the second application, we give the quantum circuits for a more practical application, breaking a symmetric cryptosystem. Although these two applications have quite different types of search criteria, they are both one-way functions and the proposed circuits can actually be generalized to any such problems. In this perspective, we conclude this paper by proposing a template of quantum circuits that is capable of searching the solution of a certain class of one-way functions. Title: Serial Addition: locally connected architectures Authors: V. Beiu, S. Aunet, J. Nyathi, R.R. Rydberg, and W. Ibrahim Abstract - This paper will briefly review nanoelectronic challenges while focusing on reliability. We shall present and analyze a series of CMOS-based examples for addition starting from the device level and moving up to the gate, the circuit, and the block level. Our analysis, backed by simulation results, on comparing parallel and serial addition shows that serial adders are more reliable and also dissipate less. Their reliability can be improved by using reliability-enhanced gates and/or other redundancy techniques (e.g., multiplexing). Additionally, the architectural technique of short-circuiting the outputs (of several redundant devices/gates/blocks) exhibits an inherent fault detection mechanism, as both transient and permanent faults could be detected based on current changes. The choice of CMOS is due to the broad design base available (but the ideas can be translated to other technologies), while addition was chosen due to its very solid background (both theoretical and practicall). The design approach will constantly be geared towards enhancing reliability as much as possible at all the levels. Theory and simulations will support the claim that a serial adder is a very serious candidate for highly reliable and low power operations. Finally, our simulations will identify the VDD range where the power-delay-product and energy-delay-product are minimized. These suggest that a reliable (redundant) solution can also be a low power one if using serial architectures, and trading speed for power (e.g., by dynamically varying the supply voltage both above and below Vth).
Sankar Basu, Editor-in-Chief, IEEE Transactions on Circuits and Systems Part I (Email: sabasu@nsf.gov)