Book Review
Circuit Analysis for Analog, Mixed-Signal and RF Designers, by Shanthi Pavan and Gabor C. Temes, Wiley-IEEE Press, 2026 | ISBN 978-1-394-27500-7
At a time when circuit simulators, numerical optimization, and the boom of AI-assisted design tools and methods, which are becoming increasingly capable of sizing, optimizing, and even synthesizing analog circuits, the scarce resource in analog design is no longer computation—it is the critical thinking and analytical intuition. Analog designers must still know which questions to ask, which constraints matter, when a result is physically meaningful, and when an apparently excellent solution is simply misleading. The Wiley-IEEE Press book titled Circuit Analysis for Analog, Mixed-Signal and RF Designers authored by Prof. Shanthi Pavan and Prof. Gabor Temes could hardly be more timely. It provides exactly the analytical understanding, practical know-how, and sound engineering judgment that analog designers need to understand circuits rather than merely accept what a simulator—or an AI engine or agent—returns.
The central strength of the book is that it builds, in a systematic, didactic, intuitive, and rigorous way, the bridge between classical circuit theory and modern design practice. The book motivates shows that circuit analysis is the language through which a real design is understood, resulting like a distillation of how experienced analog designers think. Throughout the book, mathematical rigor is consistently accompanied by physical intuition. Theory is not presented for its own sake: the reader is repeatedly shown why a result matters, how it can be used, and what it reveals about circuit behavior. Each chapter also includes problems and references, making the text well suited to teaching as well as self-study. The authors bring together exceptional expertise in analog, mixed-signal, sampled-data, filter, and data-converter design, and the text reflects decades of teaching, research, and practical insights.
Chapters 1–4 establish the book’s analytical core and progressively extend it from classical network theory to noise, nonlinearities, and RF. Chapter 1 moves from Kirchhoff’s laws, Tellegen’s theorem, small-signal analysis, and modified nodal analysis (MNA)—linked to the computational foundations of SPICE—to the bilinear form of transfer functions, the extra-element theorem, transposed MNA stamps, reciprocity and inter-reciprocity, adjoint networks, and transfer-function sensitivity, turning classical network theory into reusable design tools. Chapter 2 covers noise analysis in linear time-invariant networks, including component and spectral-density concepts, multiple noise sources, one- and two-port equivalent noise models, total integrated noise in RLC networks, the Nyquist and Bode noise theorems, impedance scaling, differential operation, and noise factor; Chapter 3 addresses weak nonlinearities through second- and third-order intermodulation, IIP2 and IIP3, cascaded stages, differential operation, transfer-curve derivatives, and the method of current injection, with applications to nonlinear feedback, nonlinear capacitors, common-collector stages, active-RC filters, and OTA-based biquads. Chapter 4 then bridges the treatment to the RF domain through distributed circuits, covering transmission lines and impedance transformation, distributed RC lines and their modeling pitfalls, scattering parameters and matrices, and vector-network-analyzer measurements, while making these RF concepts accessible to readers with primarily analog or mixed-signal backgrounds as the boundaries among these areas continue to blur.
One of the most distinctive contributions of the book comes with Chapters 5 and 6. To the best of my knowledge, this is the first textbook to provide such a systematic and detailed treatment of linear time-varying and linear periodically time-varying (LPTV) circuits within a unified circuit-analysis framework. Chapter 5 develops the subject from first principles: harmonic transfer functions, MNA stamps for periodically time-varying controlled sources, impedance and admittance, Thévenin and Norton equivalents, and the N-path principle. Chapter 6 extends the framework to reciprocity and inter-reciprocity, the frequency-reversal theorem, adjoint LPTV networks, chopped amplifiers, sampled outputs, switched-RC kernels, modulated inputs, and noise in periodically switched networks. These concepts are fundamental to mixers, chopper amplifiers, N-path filters, sampled-data circuits, and many modern RF and mixed-signal systems, yet they are usually scattered across specialized papers or treated through ad hoc arguments. Bringing them together with consistent notation, physical insight, and worked applications is a major service to the analog circuit circuits and systems community.
The final two chapters translate this analytical framework into two cornerstone application areas. Chapter 7 treats continuous-time filters, from Butterworth and Chebyshev approximation and filter realization to noise, dynamic-range scaling, fully differential processing, finite op-amp gain-bandwidth effects, and gm-C integrators and filters. Chapter 8 develops switched-capacitor circuits and filters from first principles, including integrators, filter stages, amplifiers, nonideal effects, switches, capacitor and op-amp limitations, and sampling-related noise. The closing historical discussion of switched-capacitor filters is especially fitting in a book coauthored by one of the researchers who helped shape the field.
I expect Circuit Analysis for Analog, Mixed-Signal and RF Designers to become an important reference, a unique, must-read for analog designers’ community. It is an excellent textbook for advanced undergraduate or graduate courses in electrical and electronic engineering, a valuable companion for courses in analog, mixed-signal, RF, and sampled-data design, and a practical reference for researchers and engineers working on high-performance integrated circuits. It belongs not only in university libraries, but on the desks of designers who want to understand why their circuits behave as they do. If simulation and AI can increasingly tell us what solution works, this book teaches the more enduring skill: how to understand why it works, when it will fail, and whether it should be trusted. In my view, that makes it not a retrospective book on classical circuit analysis, but a book for the future of analog and mixed-signal design.
Jose M. de la Rosa, Editor-in-Chief, IEEE TCAS-I
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Our Editors-in-Chief’s Top Picks
The Editors-in-Chief of our CASS publications have selected some noteworthy papers from the recent issues of our journals:
IEEE Transactions on Circuits and Systems I: Regular Papers
Paper 1:
F. Feyling, H. Malmberg, C. Wulff and T. Ytterdal, "Stable Filtering ADCs," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 73, no. 9, pp. 5819-5832, Sept. 2026. https://ieeexplore.ieee.org/abstract/document/11602652
Summary: Continuous-time cascaded sigma-delta modulators (MASH) and pipeline ADCs combine multiple (low-resolution) quantizers with analog filtering to achieve accurate digitization for in-band frequencies. We realized that their high-level design is limited by the underlying analytical model, which is based on increasingly fine-grained quantization in a cascaded structure. The theoretical contribution of this paper is a model that unifies and generalizes the analysis of ADCs that leverage analog filtering. The practical contribution is a methodology for designing ADCs with guaranteed stability, using any analog filter, combined with any arrangement of sub-quantizers. As an example, adding inter-stage feedback to a 1-1-1-1 MASH improves SNR for the same bandwidth, stability and hardware resources.
Paper 2:
Wenjing Ye, Wei Deng, Haikun Jia, Jingling Zhang, Linjun Gu, Fuyuan Zhao, Ruichen Wan, and Baoyong Chi, "A 0.03-to-40 GHz Reconfigurable CMOS Receiver," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 73, no. 9, pp. 6290-6303, Sept. 2026. https://ieeexplore.ieee.org/document/11570248
Summary: Future software-defined radios need to support many wireless standards across an extremely wide frequency range without relying on multiple independent receivers. This work presents a 0.03-to-40 GHz reconfigurable CMOS receiver spanning sub-GHz, microwave, FR3, and millimeter-wave bands. A frequency-partitioned dual-channel architecture independently optimizes the low- and high-frequency paths, while embedded switching enables them to share a single antenna with minimal performance degradation. The two channels also reuse the same downstream IF/baseband chain. Measurements demonstrate continuous wideband operation, a minimum noise figure of 1.92 dB, support for up to 64-QAM, and a peak data rate of 7.2 Gb/s.
IEEE Transactions on Circuits and Systems II: Express Briefs
Paper 1:
Huanting Deng; Houyi Yan; Yihan Wang; Kaizhe Guo; Dixian Zhao, “A 505–613 GHz Radiating Source With 65 GHz 3-dB EIRP Bandwidth in 65-nm CMOS Technology”, IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 73, no. 8, pp. 793 - 797, Aug. 2026. doi: 10.1109/TCSII.2026.3704610.
Summary: A 0.56-THz wideband radiating source is presented and implemented in 65-nm CMOS. The stable, wideband signal generation is achieved via an oscillator-multiplier architecture with a high multiplication factor and wideband interstage matching. Broadband transformer-based matching networks are used between the amplifier and multiplier stages to preserve the bandwidth across the chain. A compact second-harmonic trap is introduced to provide a broadband low impedance at the doubler input and improve the conversion gain. The prototype achieves a frequency tuning range of 505–613 GHz, corresponding to a fractional bandwidth of 19.3%, and a 3-dB equivalent isotropic radiated power (EIRP) bandwidth of 65 GHz. The maximum radiated power and EIRP are −10.4 dBm and 15.5 dBm, respectively. The chip consumes a dc power of 128.6 mW at the center operating frequency.
Paper 2:
Byeongcheol Yoon; Seung-Pyo Han; Junghyun Kim; Inchan Ju, “A Q-Band High-Power SiGe HBT Doherty Power Amplifier Leveraging 8-Shaped Inductor-Embedded Ultra Compact Doherty Passive Network”, IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 73, no. 8, pp. 838 - 842, Aug. 2026. doi: 10.1109/TCSII.2026.3709987.
Summary: A compact, high power Q-band SiGe HBT Doherty power amplifier (PA) for very low earth orbit (VLEO) satellite communication (SATCOM) is presented. An 8-shaped inductor-based lambda/4 impedance inverter, embedded into an output transformer (TF) balun, results in magnetic coupling cancellation (MCC) between the two, enabling to implement compact Doherty network in a single footprint. Also, an adaptive bias circuit (ABC) helps abruptly turn on and off a peaking (PK) amplifier, leading to true Doherty operation as evidenced by clear PAE peaking at 6-dB power back-off (PBO). A prototype is fabricated in SiGe HBT BiCMOS, with an active area of 0.46 mm2. It attains peak output power and power added efficiency (PAE) of 24.5 dBm and 23.9% at 38 GHz. At a 6-dB PBO, the PA achieves a PAE of 22.7%.
Paper 3:
Tingran Chen; XiaoYa Wang; Yuxuan Ran; Kaiying Yang; Yi Zhao; Kexun Cheng; Chen Li; He Zhang; Xueyan Wang; Biao Pan, “SACIM: A Synapse-Inspired Asynchronous CIM With Discharging Feedback, Dynamic Delay, and Parallelism Extension for CNN Inference”, IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 73, no. 8, pp. 768 - 772, Aug. 2026. doi: 10.1109/TCSII.2026.3693271.
Summary: This work presents a charge-domain analog compute-in-memory (ACIM) architecture, the Synapse-inspired Asynchronous CIM (SACIM), which addresses key challenges in generality, latency, and parallelism. The architecture includes three structures: a Non-Differential Decoupled (NDDC) bit-cell array for implementing negative signed weights; a Clock-free Asynchronous Controller (CFAC) to dynamically shorten latency; and an asynchronous Pulse-based Analog-to-Digital Converter (PADC) circuit with an NDDC coordination mechanism for parallelism extension. Fabricated in 40nm CMOS, the prototype achieves a peak energy efficiency of 655.78 TOPS/W and a throughput of 1180.4 GOPS.
IEEE Transactions on Circuits and Systems for Video Technologies
Paper 1:
Yimin Fu, Runqing Yang, Zhunga Liu, Michael K. Ng. "Adaptive Mixture-of-Experts Distillation for Cross-Satellite Generalizable Incremental Remote Sensing Scene Classification," IEEE Trans. on Circuits and Systems for Video Technology, vol.36, no.1, pp.233-247, Jan. 2026. doi: 10.1109/TCSVT.2025.359827.
This paper proposes adaptive mixture-of-experts distillation (AMoED) for cross-satellite generalizable incremental remote sensing scene classification (CS-GIRSSC). Specifically, AMoED adopts a high-level semantic learning pipeline, in which new knowledge is acquired through the coordinated guidance of multiple domain-specific experts, rather than directly from raw data. This pipeline prevents the model from being exposed to large volumes of newly emerging data, thereby alleviating the erasure of previous knowledge when adapting to new data distributions. Besides, the adaptive mixture of domain-specific experts facilitates the formation of universal class concepts, which exhibit strong generalizability across different domains. During the learning process, an equi-partite subset is constructed for knowledge acquisition and consolidation, accompanied by a shallow style-mixing operation to mitigate the interference of domain discrepancies. Extensive experiments have been conducted on four remote sensing scene classification datasets, and the method proposed in this paper consistently shows state-of-the-art performance across various scenarios and settings. The code has been also made available by the authors at https://github.com/fuyimin96/AMoED
Paper 2:
Xiao Wang, Chao Wang, Shiao Wang, Xixi Wang, Zhicheng Zhao, Lin Zhu. "MambaEVT: Event Stream-Based Visual Object Tracking Using State Space Model," IEEE Trans. on Circuits and Systems for Video Technology, vol.36, no.1, pp.278-291, Jan. 2026. doi: 10.1109/TCSVT.2025.3588533.
This paper proposes a Mamba-based visual tracking framework that adopts the state space model with linear complexity as a backbone network. The search regions and target template are fed into the vision Mamba network for simultaneous feature extraction and interaction. The output tokens of search regions will be fed into the tracking head for target localization. More importantly, a dynamic template update strategy is introduced into the tracking framework using the Memory Mamba network. By considering the diversity of samples in the target template library and making appropriate adjustments to the template memory module, an effective dynamic template can be integrated. The effective combination of dynamic and static templates allows the proposed Mamba-based tracking algorithm to achieve a good balance between accuracy and computational cost on multiple large-scale datasets, including EventVOT, VisEvent, and FE240hz. The source code and checkpoint of this work have been released on https://github.com/Event-AHU/MambaEVT
Overview of the proposed pure Mamba-based visual object tracking using an event camera, termed MambaEVT. The vision Mamba based backbone network performs feature extraction, interaction and fusion, simultaneously. It ensures the tracker achieves good performance and lowers computational cost. The learnable Memory Mamba for dynamic template generation makes the tracker more robust to significant appearance variation.
Paper 3:
Nian Wang, Zhigao Cui, Yanzhao Su, Yunwei Lan, Yuanliang Xue, Cong Zhang. "Weakly Supervised Image Dehazing via Physics-Based Decomposition," in IEEE Trans. on Circuits and Systems for Video Technology, vol.36, no.1, pp.637-652, Jan. 2026, doi: 10.1109/TCSVT.2025.3596024.
This paper proposes a weakly supervised image dehazing (WSID) model via physics-based decomposition (PBD). The proposed approach estimates atmospheric light, scattering coefficient and scene depth of real haze input to effectively capture the illumination information and haze distribution to recover a preliminary dehazed image by minimizing reconstruction loss. With this constraint, a subtly discrete wavelet discriminator (DWD) is designed to effectively improve the generalization to real scene from both spatial and frequency aspect under the supervision of unpaired real clear image. The PBD is a purely data-driven model freeing from any manual setting or partially correct prior, thus simultaneously ensuring the realness and visibility of dehazed images. Experiments on seven benchmarks have been reported in the paper showing the strong generalization ability of the proposed PBD, which achieves SOTA dehazing performance with realistic details. The code has been made available by the authors at the following link at https://github.com/NianWang-HJJGCDX/PBD
Workflow of the PBD proposed in this paper. First, four generators are used to yield the dehazed image Jout, scattering coefficient β, scene depth D, global atmospheric light A. The β and D capture the haze distribution of input real haze image Ireal and obtain a refined transmission map T. Reconstruction loss is used to constrain the structure information of these parameters. Then DWD improves the generalization ability of Jout and makes it fit in various real haze scenes via the adversarial training from both spatial and frequency aspect.
IEEE Journal on Emerging and Selected Topics in Circuits and Systems
Paper 1:
V. K. Bose, R. V. Joshi, Y. Cao and B. J. Kailath, "ShiftMUX: Reconfigurable 4:1 MUX-Based In-Memory Shifter for Multiplication-Less Deep Neural Network Accelerations," in IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 16, no. 2, pp. 327-337, June 2026. https://ieeexplore.ieee.org/document/11318555
Summary: This paper presents ShiftMUX, a reconfigurable 4:1 multiplexer (MUX)-based in-memory computing (IMC) architecture for multiplier-less deep neural network (DNN) acceleration. The proposed design completes its operation in only three cycles, compared with at least ten cycles in prior approaches. Beyond basic logic, ShiftMUX supports complex functions such as full adder, full subtractor, and comparator, eliminating the need for separate mapping and control peripherals. When cascaded in a crossbar, multiple MUX units realize N -bit shift operations including logical, arithmetic, circular, and universal shifts enabling efficient power-of-two multiplications for quantized DNNs. Circuit-level simulations in 45 nm technology show write energy of 32 pJ, read delay of 9.14 ps, and a total energy consumption of 240 pJ for a 4-bit multiplier, outperforming state-of-the-art designs. A Vision Transformer model exhibits only a + 2.66% accuracy deviation with shift-based multiplication, confirming the suitability of ShiftMUX for modern AI models. Moreover, the architecture reduces computation overhead by more than 90%, requiring only N+log2 (N)+2 cycles, and achieves up to 9×speedup in multiplication. ShiftMUX thus provides a scalable, reconfigurable, and energy-efficient solution for low-latency DNN acceleration in edge and high-performance computing systems.
Paper 2:
Y. -X. Zhang, S. Yang, Y. -H. Ren, S. Chen and P. Zhang, "In-Memory Computing-Based Ultra-Efficient Massive MIMO Precoding: Memristor Crossbar Circuits, Conductance Mapping Strategies, and Programming Latency Estimation," in IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 16, no. 2, pp. 525-537, June 2026. https://ieeexplore.ieee.org/document/11316487
Summary: Massive MIMO is a key technology for 5G and future 6G wireless systems, but linear precoding methods such as zero-forcing and minimum mean square error precoding require matrix inversion, which creates substantial latency and energy overhead in baseband processing. This paper presents an in-memory computing solution based on memristor crossbar circuits for ultra-efficient massive MIMO precoding. The proposed architecture supports both ZF and MMSE precoding in a unified circuit and enables fast one-step computation without complex timing control. To address practical device limitations, the work develops an optimized matrix-to-conductance mapping strategy that jointly considers memristor conductance constraints and precoding-matrix statistics, reducing relative computation error by more than 60% compared with a baseline mapping scheme. It also introduces a probabilistic programming-latency model that captures potentiation and depression dynamics and provides closed-form latency estimates validated by Monte Carlo simulations. System-level results show that the proposed circuit achieves BER close to 64-bit floating-point precoding while providing over 100× improvements in energy and area efficiency compared with baseline commercial GPUs.
Paper 3:
W. -J. Tsai et al., "A Page-Buffer and Fail-Bit Counter-Based In-Memory Computing Platform for 3-D NAND Flash Memory," in IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 16, no. 2, pp. 617-628, June 2026. https://ieeexplore.ieee.org/document/11369267
Summary: We propose an in-memory computing platform for 3D NAND Flash memory. By re-purposing the existing page buffers and fail-bit counters in the NAND Flash chip, diverse in-memory computing applications such as bulk bitwise operation, in-memory search, and vector similarity search can be realized. The re-design cost is minimized, and its operation is almost comparable to the original NAND Flash’s program, erase, and read operations. It is robust against process, voltage, and temperature variations. By reducing the need for huge and frequent data transfers between storage and the processor, latency and energy efficiency are greatly improved. This design presents an attractive and promising option for in-memory computing applications in NAND Flash memory. Furthermore, it can be applied to other storage or memory devices that possess the page buffers and fail-bit counters suitable for re-purposing..
IEEE Open Journal of Circuits and Systems
Paper 1:
E. Sacchi et al., "8-Channel CMOS Chip for Real-Time Control of Integrated Silicon Photonic Processors," in IEEE Open Journal of Circuits and Systems, vol. 7, pp. 206-217, 2026. https://ieeexplore.ieee.org/document/11304253
Summary: Light moves fast, but programmable photonic processors still need electronics clever enough to keep them on course. In this paper, Sacchi and colleagues introduce an eight-channel CMOS controller that continuously monitors and adjusts silicon photonic interferometers in real time. Using two controller chips, the team independently steered all 15 interferometers in a 16-channel photonic mesh, recovering the optimal optical path from a random starting point in roughly 10–15 milliseconds. This boosted output power by about 23 dB. Even more impressively, the system compensated for simulated atmospheric turbulence and restored free-space optical links carrying 25-Gbit/s and 50-Gbit/s signals. By replacing bulky FPGA-based control hardware with compact, parallel feedback electronics, this work brings scalable, self-correcting photonic processors closer to practical deployment in communications, computing, sensing, and beyond.
Paper 2:
A. Maclellan, L. H. Crockett and R. W. Stewart, "RFSoC Modulation Classification With Streaming CNN: Data Set Generation & Quantized-Aware Training," in IEEE Open Journal of Circuits and Systems, vol. 6, pp. 38-49, 2025. https://ieeexplore.ieee.org/document/10772713
Summary: This work presents a dynamic amplifier that achieves −52 dB in total harmonic distortion through an analog technique by which the expanding and compressing nonlinearities in the input transistors cancel one another. A pipeline-SAR analog-to-digital converter incorporating the linearized dynamic amplifier in both the input buffer and the first residue amplifier stage was designed and fabricated using the GlobalFoundries 22nm fully depleted silicon-on-insulator process.
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IEEE CAS Magazine Third Quarter Issue 2026
IEEE Circuits and Systems (CAS) Magazine publishes original review articles and other articles that are of broad interest to the Circuits and Systems Society community. Interested authors are invited to send a three to four page White Paper first to the Editor-in-Chief, Prof. Keshab K. Parhi, by email here. If invited, they can submit a Full Paper at the Author Portal at the link below. CAS Magazine will continue to publish articles related to CAS Society Outreach. In addition, CAS Magazine also publishes articles related to education (such as tricks in solving problems and short lecture notes), conference highlights, chapter highlights, applications, and standards. Please feel free to submit articles that are of broad interest to the members of the CAS Society. For more information, please visit the IEEE Circuits and Systems Magazine on the CASS website.
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Latest Tables of Contents of CAS Sponsored Journals
The latest issues of our CAS sponored journals have been published and the tables of contents can be accessed through the following links:
- IEEE Transactions on Circuits and Systems I: Regular Papers
- IEEE Transactions on Circuits and Systems II: Express Briefs
- IEEE Transactions on Circuits and Systems for Video Technology
- IEEE Journal on Emerging and Selected Topics in Circuits and Systems
- IEEE Circuits and Systems Magazine
- IEEE Transactions on Biomedical Circuits and Systems
- IEEE Design and Test Magaz