SOCIETY NEWS
Chapter of the Year 2006:
The Shanghai CAS Chapter
Since its establishment in 2001, the IEEE CAS Shanghai Chapter has received a lot of kind help from the IEEE Beijing Section and the IEEE CAS former President Prof. Ruywen Liu. Under the leadership of the founding President Prof. Zhenya He, the IEEE CAS Shanghai Chapter has organized a lot of academic activities enthusiastically, and has held international conferences that focused on neural networks and signal processing for a number of years. In 2005, 11 technical meetings were organized by the Chapter, while many experts from USA, Japan and Hong Kong were invited to visit or give lectures in universities in the Shanghai area. For instance, in May 2005, the IEEE International Workshop on VLSI Design and Video Technology was organized successfully with the help of IEEE CAS Society. Some international experts were invited to present invited technical reports, including Prof. S.Y. Kung from Princeton University, Prof. N. Fujii from Tokyo Institute of Technology, Prof. W.C. Siu from Hong Kong Polytechnic University, Prof. R.M. Mersereau from Georgia Institute of Technology, Prof. Ray T. Chen from Texas University, etc. The Workshop was held in the beautiful city of Suzhou which is close to Shanghai, and was supported by a number of US and Japan based IC manufacturers within the Suzhou Industrial Park. It also produced positive influences in promoting the IC research and development around the Yangzi River Delta area and expanding the academic influence of the IEEE CAS society in eastern China. The Shanghai area is one of the most active areas in China, with many good universities and research institutes and lots of excellent engineers in circuit design and development. The IEEE CAS Shanghai Chapter also makes a lot of efforts in pushing the IEEE CAS membership development. Many reports were published to introduce the IEEE CAS Society and its activities to a wide range of audience. At the same time, we realize that we are still a young chapter compared with other IEEE CAS chapters in other parts of the world, and we still have a lot to do. The Chapter-of-the-Year Award is the best encouragement to our work. We would like to express our best regards to those who care and help us all through, and will continue to promote the membership development and academic activities in the best way we can.
Design Automation Conference 2007 Program Highlights
This year’s technical program consists of 161 selected papers out of 713 submissions, and is supplemented by 7 special sessions, 7 tutorials, 8 panels and 17 pavilion panels. The result is an exciting program, targeted to design engineers, management, developers and researchers, that showcases the latest new advances in the area of electronic design automation.
The technical theme for this year’s DAC is automotive electronics: an all-day track on Wednesday includes a special session, invited talks, a panel, and regular papers. Modern automobiles have an incredible array of electronic systems: engine management, satellite navigation, adaptive cruise control and many more. The increasing trend in auto electronics shows few signs of abating: it has been estimated that electronics will account for as much as 40% of a car's bill-of-materials by the end of this decade. The modern car can truly be described as a "networked computing platform," and the theme will highlight this issue in the context of electronic design automation.
The program this year includes a new WACI (wild and crazy ideas) session. The papers in this session encourage out-of-the-box thinking and are designed to promote discussions among attendees during and after the session.The technical sessions are divided into ten tracks: Analog/Mixed-Signal/RF and Simulation, Automotive Electronics, Business, DFM and the Manufacturing Interface, Interconnect and Reliability, Low Power Design, New and Emerging Technologies, Physical Design, Synthesis and FPGA, System Level and Embedded Design, and Verification and Test.
A major theme this year includes a strong focal point built around system-level design, including system-level communication issues aimed at designing the communication infrastructure of complex systems-on-chip, sessions that highlight industrial applications of ESL methods, MPSoC design, and transaction level modeling and 1000 core chips. Sessions in the area of embedded systems present the latest in embedded hardware and software design methods,
Design for manufacturability issues are prominent throughout the program. This includes regular sessions on process-aware physical design, statistical timing analysis, bridging the gap with silicon and modeling the impact of technology of design. These are supplemented by special sessions on silicon measurement and the design-manufacturing interface.
Low power is a prominent design consideration, and several sessions in the technical program focus on issues in this area. This year's selection of papers on power analysis and low power design covers a broad range of topics of wide interest for practical applications and workflows, with sessions dedicated to issues related to leakage power and implications of design variability on full-chip leakage power, on circuit-level approaches for low power design, and on tools and methodologies of interest to system-level design.
Another strong component of the program is in the area of verification: this year's program includes some outstanding papers on improving the verification process, ranging from theoretical results on the core computational engines of verification tools to practical, "best practices" case studies on the successful use of cutting-edge verification methodologies.
The technical paper presentations on Tuesday through Thursday are complemented by 7 tutorial presentations on Monday and Friday. These are presented by experts in the field, and cover themes such as DFM and variability, system level design, formal verification, reliability under soft errors, and beyond-the-die issues. The 7 hands-on tutorials are in the area of DFM.
The business track is driven by an all-day track on Tuesday, beginning with a morning keynote, and continuing with an all-day management seminar presented by a group of luminaries: Geoffrey Moore, Raul Camposano and Jim Smith.
An array of panels spread throughout the program allow for free-form discussions headed by leaders in the field, addressing emerging and important areas in the field of EDA. The panels cover topics such as EDA megatrends under shortening consumer cycles, handoffs between design and manufacturing, early power-aware design, transaction-level modeling, IP issues, multicore design, and challenges in functional verification. Pavilion panels on the exhibit floor lay the basis for more free-flowing and informal discussions. Topics of this year’s panels include trends in EDA, managing mixed-signal designs, DFM, system-level wireless design, anticipating the next killer app, and many more.
S. Sapatnekar (Email: sachin@ece.umn.edu), Univ. of Minnesota, MN, USA, and L. Stok (Email: leonstok@us.ibm.com), IBM Corp., NY USA.