IEEE Circuits and Systems Society Newsletter | Volume 18 | Issue 3 | June 2024 | CURRENT/PAST ISSUES

PUBLICATION NEWS


Our Editors-in-Chief’s Top Picks

The Editors-in-Chief of our CASS publications have selected some noteworthy papers from the recent issues of our journals:


IEEE Journal of Emerging and Selected Topics in Circuits and Systems

Paper 1

C. Wang, P. -C. Chiu, C. -L. Ko, S. -H. Tseng and C. -H. Li, "A 340-GHz THz Amplifier-Frequency-Multiplier Chain With 360° Phase-Shifting Range and its Phase Characterization," IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 14, no. 1, pp. 52-66, March 2024, doi: 10.1109/JETCAS.2023.3345358. https://ieeexplore.ieee.org/document/10367994

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Summary: In this paper, the authors show a THz compact amplifier-frequency-multiplier chain (AMC) offering a full 360° phase shifting range for 6G phased-array applications and a measurement setup for characterizing the phase of a THz signal. The novel AMC comprises an 85-GHz phase-shifter-embedded (Δφ-embedded) power amplifier (PA) simultaneously supporting power amplification and phase-shifting functions and a high-output-power 340-GHz frequency quadrupler (FQ) incorporating an optimal output harmonic impedance matching network (IMN). Implemented in a 40-nm CMOS technology without ultra-thick metal layers available, the THz AMC achieves an output power of –4.4 dBm and a conversion gain of 0.7 dB at 324 GHz while providing a tunable output phase over 360° within the 324 to 346 GHz frequency range.

Paper 2

W.-C. Chen and H. -Y. Chang, "Design and Analysis of a V-Band CMOS Sextuple SILVCO Using Transformer and Cascade-Series Coupling With a Frequency-Tracking Loop," IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 14, no. 1, pp. 75-87, March 2024, doi: 10.1109/JETCAS.2023.3329430. https://ieeexplore.ieee.org/document/10304163

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Summary: A low-phase-noise local oscillator (LO) is a crucial component in communication systems. However, the design challenge of the LO significantly increases as the operating frequency rises. This paper focuses on the design and analysis of a V-band CMOS sextuple sub-harmonically injection-locked voltage-controlled oscillator (SILVCO) with a frequency-tracking loop (FTL). The SILVCO with FTL is implemented using a 90-nm CMOS process. With a sub-harmonic number of 6 and a DC power consumption of 23 mW, the measured output frequency ranges from 50.8 to 53.4 GHz, achieving a differential output power close to 0 dBm. The measured phase noise at a 1 MHz offset and the rms jitter integrated from 1 kHz to 10 MHz are both lower than -109.4 dBc/Hz and 43 fs, respectively


Paper 3

L. Chen, L. Chen, D. Sun, Y. Sun, Y. Pan and X. Zhu, "A 39 GHz Doherty-Like Power Amplifier With 22dBm Output Power and 21% Power-Added Efficiency at 6dB Power Back-Off," IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 14, no. 1, pp. 88-99, March 2024, doi: 10.1109/JETCAS.2024.3351075. https://ieeexplore.ieee.org/document/10382503

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Summary: The design of a Doherty-like power amplifier for millimetre-wave (mm-wave) applications is presented in this work. The designed power amplifier employs a novel symmetrical load-modulated balanced amplifier (S-LMBA) architecture. The S-LMBA is fabricated in a 45-nm CMOS SOI technology. At 39 GHz, a 22.1 dBm saturated output power with a maximum power-added efficiency (PAE) of 25.7% is achieved. An average output power of 13.1 dBm with a PAE of 14.4% at an error vector magnitude above -22.5 dB and adjacent channel power ratio of -23 dBc is also achieved, when a 200 MHz single carrier 64-quadrature-amplitude-modulation signal is used. Including all testing pads, the footprint of the designed S-LMBA is only 1.56 mm2.


IEEE Transactions on Circuits and Systems for Video Technology

Paper 1

Changshuo Wang, Xin Ning, Weijun Li, Xiao Bai, and Xingyu Gao. “3D Person Re-Identification Based on Global Semantic Guidance and Local Feature Aggregation,” IEEE Transactions on Circuits and Systems for Video Technology, vol. 34, no. 6, June 2024. https://ieeexplore.ieee.org/document/10301577

Summary: Most existing person re-identification (Re-ID) methods learn pedestrian feature representations from images, so ignoring the real 3D human body structure and the spatial relationship between the pedestrians and interferents. To address these limitations in the current literature of person Re-ID, this paper proposes a new point cloud Re-ID network, named PointReIDNet, designed to obtain 3D shape representations of pedestrians from point clouds of 3D scenes. The model consists of two modules: a global semantic guidance module and a local feature extraction module. The global semantic guidance module is designed to enhance the point cloud feature representation in similar feature neighborhoods and to reduce the interference caused by 3D shape reconstruction or noise. A space cover convolution (SC-Conv) is also proposed to efficiently represent point clouds by encoding information on human shapes in local point clouds. Results obtained on four holistic person Re-ID datasets, one occlusion person Re-ID dataset and one point cloud classification dataset exhibit significant improvements over point-cloud based person Re-ID methods.

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Figure (right): (a) A general person re-identification method based on 2D images; (b) The method proposed in this paper to learn pedestrian features from a 3D space.




Paper 2:

Jun Tang, Chenyan Lu, Zhengxue Liu, Jiale Li, Hang Dai, and Yong Ding. "CTVSR: Collaborative Spatial–Temporal Transformer for Video Super-Resolution,” IEEE Transactions on Circuits and Systems for Video Technology, vol. 34, no. 6, June 2024. https://ieeexplore.ieee.org/document/10347267

Summary: This paper proposes a Collaborative Transformer for Video Super-Resolution (CTVSR). The proposed method integrates the strengths of Transformer-based and recurrent-based models by concurrently assimilating the spatial information derived from multi-scale receptive fields and the temporal information acquired from temporal trajectories. In particular, a Spatial Enhanced Network (SEN) is proposed with two key components: Token Dropout Attention (TDA) and Deformable Multi-head Cross Attention (DMCA). TDA focuses on the key regions to extract more informative features, and DMCA employs deformable cross attention to gather information from adjacent frames. A Temporal-trajectory Enhanced Network (TEN) is also introduced that computes the similarity of a given token with temporally related tokens in the temporal trajectory. Experiments on four widely used VSR benchmarks, show the CTVSR method proposed in this paper is capable of achieving competitive performance with relatively low computational consumption and high forward speed.

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Figure (above): Overview of the Collaborative Transformer for Video Super-Resolution (CTVSR) approach proposed in this paper. The Spatial Enhanced Network (SEN) leverages Token Dropout Attention (TDA) and Deformable Multi-head Cross Attention (DMCA) to integrate local details and global information and thus derive spatial features. Inside the TEN module, two temporal trajectories are visualized using green color and orange color, respectively. The size of those circles in TEN represents the search range of the colored tokens. Then, analysis is conducted on the green token; the orange token indicates the useful search range is distinct for every token across time. Flow is produced by a pre-trained optical flow estimation model (SpyNet). Res(·) stacks several residual blocks to reconstruct details.


Paper 3:

Min Cao, Yang Bai, Ziqiang Cao, Liqiang Nie, and Min Zhang. "Efficient Image-Text Retrieval via Keyword-Guided Pre-Screening,” IEEE Transactions on Circuits and Systems for Video Technology, vol. 34, no. 6, June 2024. https://ieeexplore.ieee.org/document/10342878

Summary: This paper proposes a simple and effective keyword-guided pre-screening framework for image-text retrieval. The image and text data are converted into keywords and keyword matching is performed across the modalities to exclude a large number of irrelevant gallery samples prior to the retrieval network. The keyword prediction is transferred into a multi-label classification problem and a multi-task learning scheme is proposed by appending the multi-label classifiers to the image-text retrieval network. This aims to obtain a lightweight and high-performance keyword prediction. For keyword matching, the inverted index from the search engine is introduces and thus a win-win situation is created on both time and space complexities for the pre-screening. Experiments on the Flickr30K and MS-COCO, verify the effectiveness of the proposed framework: with only two embedding layers it achieves O(1) querying time complexity, while improving the retrieval efficiency and maintaining performance, when applied prior to common image-text retrieval methods.

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Figure (above): On the left the skeleton of various image-text retrieval methods is shown for the example case of text-to-image retrieval. On the right, the methods on the left are compared. Rank-1 denotes the expectation of correct match at the 1st in the ranking list (performance index) and Speedup refers to the retrieval acceleration from the acceleration module (efficiency index). Time and Para represent the online running time and the number of parameters of the acceleration module, respectively. These results are computed based on the one-stream network ViLT and two-stream network ALBEF0 on MS-COCO. In the framework proposed in this paper, the classification by multi-task learning on the ALBEF is proposed.


IEEE Transactions on Biomedical Circuits and Systems

Paper 1

M. Sporer et al., "NeuroBus - Architecture for an Ultra-Flexible Neural Interface," IEEE Transactions on Biomedical Circuits and Systems, vol. 18, no. 2, pp. 247-262, April 2024, doi: 10.1109/TBCAS.2024.3354785. https://ieeexplore.ieee.org/document/10400847

Paper 2

S. Hosur, Z. Kashani, S. K. Karan, S. Priya and M. Kiani, "MagSonic: Hybrid Magnetic-Ultrasonic Wireless Interrogation of Millimeter-Scale Biomedical Implants With Magnetoelectric Transducer," IEEE Transactions on Biomedical Circuits and Systems, vol. 18, no. 2, pp. 383-395, April 2024, doi: 10.1109/TBCAS.2023.3334166. https://ieeexplore.ieee.org/document/10321651

Paper 3

D. Mukherjee, S. K. Rainu, N. Singh and D. Mallick, "A Miniaturized, Low-Frequency Magnetoelectric Wireless Power Transfer System for Powering Biomedical Implants," in IEEE Transactions on Biomedical Circuits and Systems, vol. 18, no. 2, pp. 438-450, April 2024, doi: 10.1109/TBCAS.2023.3336598. https://ieeexplore.ieee.org/document/10328696


IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Paper 1

R. Balas, A. Ottaviano and L. Benini, "CV32RT: Enabling Fast Interrupt and Context Switching for RISC-V Microcontrollers," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 32, no. 6, pp. 1032-1044, June 2024, doi: 10.1109/TVLSI.2024.3377130 
https://ieeexplore.ieee.org/document/10477942

Summary: This paper discusses the increasing adoption of RISC-V processors in the embedded world, highlighting their need for real-time constraints, flexibility, predictability, and fast event handling. The paper compares RISC-V processors to more mature proprietary architectures like ARM Cortex-M and TriCore, noting that RISC-V lags in interrupt handling. The standard RISC-V core local interruptor (CLINT) is limited in configurability for interrupt prioritization and preemption. To address this, the RISC-V core local interrupt controller (CLIC) specification introduces preemptible, low-latency vectored interrupts with optional extensions to improve latency. The paper presents the implementation of a CLIC for the CV32E40P, an open-source 32-bit RISC-V core, and its enhancement with a custom extension called fastirq, achieving interrupt latency as low as six cycles. The enhanced core, named CV32RT, is the first fully open-source RV32 core with interrupt-handling features comparable to ARM Cortex-M and TriCore. The extensions also improve task context switching in real-time operating systems (RTOSs).


Paper 2

L. Zhou et al., "Better-Than-Worst-Case: A Frequency Adaptation Asynchronous RISC-V Core With Vector Extension," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 32, no. 6, pp. 1045-1057, June 2024, doi: 10.1109/TVLSI.2024.3375350. https://ieeexplore.ieee.org/document/10475190

Summary: This paper proposes a fully digital design method for frequency adaptation in asynchronous bundled-data (BD) circuits. The method is straightforward, effective, widely applicable, and independent of asynchronous controllers, allowing automatic frequency adaptation to improve performance and reduce power consumption, achieving better-than-worst-case scenarios. To verify this method, an asynchronous RISC-V processor with a vector acceleration extension was designed using both the TSMC 65-nm process and a field-programmable gate array (FPGA) platform. Postlayout simulation results show that, compared to its synchronous version, the asynchronous processor achieves a 10% speed improvement (from 227.3 to 250 MHz) and a 37% power reduction (from 135 to 85 μW/MHz) under ideal conditions. Even under worst-case conditions, the asynchronous processor matches the synchronous processor's performance while still reducing power consumption by 29% (from 133 to 95 μW/MHz). On the FPGA platform, the asynchronous processor also demonstrates higher speed and lower power consumption.


Paper 3

X. Zheng, M. Cheng, J. Chen, H. Gao, X. Xiong and S. Cai, "BSSE: Design Space Exploration on the BOOM With Semi-Supervised Learning," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 32, no. 5, pp. 860-869, May 2024, doi: 10.1109/TVLSI.2024.3368075. https://ieeexplore.ieee.org/document/10454021

Summary: This paper highlights the challenge of exploring the vast and complex RISC-V microarchitecture design space. The authors propose the Berkeley Out-of-Order Machine Semi-Supervised Explorer (BSSE) framework which leverages semi-supervised learning and parallel emulation to expedite and optimize the design space exploration of RISC-V microarchitectures. The process begins with constructing an initial training dataset using the microarchitecture experimental design sampling (MEDS) method. It then employs a co-training-style k-nearest neighbors (Co-KNN) model to map microarchitecture features to architectural metric values. The trained Co-KNN model aids in searching for a Pareto-optimal set through parallel emulation. A distance-based method then selects a designer-preferred microarchitecture from this set. Extensive experiments on the Berkeley Out-of-Order Machine (BOOM) demonstrate that BSSE can identify a superior Pareto-optimal set more efficiently than state-of-the-art methods and can find microarchitectures that match or surpass the performance of existing manually designed BOOM microarchitectures.


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IEEE Circuits and Systems Magazine Latest Feature Articles: Special Issue on the 75th Anniversary of the IEEE CAS Society

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  1. Past, Present, and Future of CASS Educational Programs and Initiatives
    Fakhrul Zaman Rokhani, Xinmiao Zhang, Rajiv V. Joshi, Ricardo Reis, Victor Grimblatt, Kea-Tiong Tang, Yongfu Li, Amara Amara, and Manuel Delgado-Restituto
  2. Superconductive Electronics: A 25-Year Review
    Rassul Bairamkulov and Giovanni De Micheli
  3. Cryogenic CMOS Design for Qubit Control: Present Status, Challenges, and Future Directions
    Sudipto Chakraborty and Rajiv V. Joshi
  4. PCI-Express: Evolution of a Ubiquitous Load-Store Interconnect Over Two Decades and the Path Forward for the Next Two Decades
    Debendra Das Sharma
  5. Fast Settling Phase-Locked Loops: A Comprehensive Survey of Applications and Techniques
    Zeeshan Ali, Pallavi Paliwal, Meraj Ahmad, Hadi Heidari, and Shalabh Gupta
  6. A Different View of Sigma-Delta Modulators Under the Lens of Pulse Frequency Modulation
    Victor Medina, Pieter Rombouts, and Luis Hernandez-Corporales


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