Our Editors-in-Chief’s Top Picks
The Editors-in-Chief of our CASS publications have selected some noteworthy papers from the recent issues of our journals:
IEEE Transactions on Circuits and Systems II: Express Briefs
Paper 1:
Yao Li, Yijun Cui, Shuming Guo, Jiang Li, Ruilin Zhang, Chongyan Gu, Chenghua Wang, and Weiqiang Liu, “A 0.071 pJ/Bit Flexible Multi-Mode Logic-Compatible Multiple-Time Programmable (MTP) Memory-Based PUF,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 72, no. 7, pp. 953-957, Jul. 2025. doi: 10.1109/TCSII.2025.3574130
https://ieeexplore.ieee.org/document/11016056
Summary: In this brief, a novel high energy efficiency flexible multi-mode logic-compatible multiple-time programmable (MTP) memory-based PUF is proposed for key generation. The proposed PUF utilizes random distributions of read current in programming MTP cells as its entropy source. Moreover, it features a flexible multi-mode reconfigurable function, which is achieved by switching the programming/erasing (P/E) states to update the read current. The proposed PUF is manufactured in a 153-nm standard CMOS process. The proposed PUF achieves high-security performance of ~100% stability and 99.42% reliability while consuming an average core energy of only 0.071pJ/bit. Intra-HD is 0.58%, inter-HD is 49.70%, and reconfigure-HD is 48.28%.
Paper 2:
Shiping Zheng, Yun Wang, Ziyang Deng, Chen Jiang, Hongtao Xu, “A 22.5∼28.5-GHz Low-Amplitude-Variation Low-Phase-Error Hybrid Phase Shifter Using Flatness Enhancement Techniques for 5G NR in 40-nm CMOS”, IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 72, no. 6, pp. 813 – 817, May. 2025.
doi: 10.1109/TCSII.2025.3563519.
https://ieeexplore.ieee.org/document/10974670
Summary: This brief presents a hybrid phase shifter (PS) that integrates a three-stage switch-type phase shifter (STPS) and a one-stage reflect-type phase shifter (RTPS). The STPS utilizes a flatness-enhanced π -network topology to reduce phase error and insertion loss (IL) variation by eliminating feedback and resonant capacitors. The RTPS enables continuous phase shifting with a 4-bit capacitor array and varactor. The proposed hybrid PS achieves an IL variation of ±0.7 dB and an RMS phase error of 0.3° to 1.2° in the 22.5∼28 .5 GHz range. Compared to existing designs, the hybrid PS offers superior performance in phase accuracy, IL variation, and area efficiency, with a compact area of 151×342 μm2 , fabricated using standard 40nm CMOS technology.
Paper 3:
Zhuoheng Xie, Yue Feng, Bo Huang, Zihan Zhang, Heng Zhao, Lan Liu, Zhihao Liu, Zhigang Li, Xiulong Wu, “A Ku-Band Broadband 8-Channel 8-Beam Phased-Array Receiver With Polarization Agility and Beam Reconfiguration for SATCOM Applications”, IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 72, no. 7, pp. 893 - 897, Jul. 2025.
doi: 10.1109/TCSII.2025.3578020.
https://ieeexplore.ieee.org/document/11029074
Summary: This brief presents a Ku-band broadband 8-channel 8-beam phased-array receiver with polarization agility and dynamic beam reconfiguration, addressing the growing demand for Low Earth Orbit (LEO) and high-throughput satellite communications (SATCOM). The receiver chip integrates 32 independently controlled amplitude and phase channels, utilizing an innovatively designed reconfigurable power divider network to flexibly support single-beam, dual-beam, four-beam, and eight-beam modes, while enabling dynamic selection between horizontal and vertical polarization. Measurement results demonstrate a wide operational frequency range from 10 GHz to 15 GHz, achieving a remarkable channel gain of 24.5 dB and an input 1-dB gain compression point (IP1dB) exceeding 15.8 dBm. Fabricated using a 0.18 μ m SiGe Bi-CMOS process, the chip features a compact area of 6.7×5.3mm2 and a total power consumption of less than 465 mW.
IEEE Transactions on Circuits and Systems for Video Technologies
Paper 1:
H. Ho-Ching Iu, U. Erkan, C. Simsek, A. Toktas, Y. Cao, "A 3D Memristive Cubic Map With Dual Discrete Memristors: Design, Implementation, and Application in Image Encryption," IEEE Transactions on Circuits and Systems for Video Technology, vol. 35, no. 8, pp. 7706-7718, Aug. 2025, doi: 10.1109/TCSVT.2025.3545868.
This paper introduces a novel discrete chaotic system employing dual memristors, named the 3D memristive cubic map with dual discrete memristors (3D-MCM). The 3D-MCM system demonstrates richer and more intricate dynamical behaviors compared to its single-memristor counterparts, as verified through bifurcation diagrams, Lyapunov exponent spectra, and complexity analyses. Notably, the system exhibits coexisting attractors, substantially enhancing its dynamical complexity. Hardware implementation of the 3D-MCM attractors confirms its feasibility for industrial applications. To illustrate the system potential in encryption tasks, this study integrates the quaternary-based permutation and dynamic emanating diffusion (QPDED-IE) scheme with the 3D-MCM for image encryption. Experimental results demonstrate that the QPDED-IE scheme based on the 3D-MCM exhibits strong diffusion and confusion properties, effectively resisting cryptanalytic attacks
Paper 2:
X. Min, Y. Gao, Y. Cao, G. Zhai, W. Zhang, H. Sun, "Exploring Rich Subjective Quality Information for Image Quality Assessment in the Wild," in IEEE Transactions on Circuits and Systems for Video Technology, vol. 35, no. 8, pp. 7778-7791, Aug. 2025, doi: 10.1109/TCSVT.2025.3544659.
This paper propose a novel Image Quality Assessment (IQA) method named RichIQA to explore the rich subjective rating information beyond MOS to predict image quality in the wild. RichIQA is characterized by two novel designs: 1) a three-stage image quality prediction network, which exploits the powerful feature representation capability of the Convolutional vision Transformer (CvT) and mimics the short-term and long-term memory mechanisms of human brain; 2) a multi-label training strategy in which rich subjective quality information like MOS, SOS and DOS are concurrently used to train the quality prediction network. Powered by these two novel designs, RichIQA is able to predict the image quality in terms of a distribution, from which the mean image quality can be subsequently obtained. Experimental results verify that the three-stage network is tailored to predict rich quality information, while the multi-label training strategy can fully exploit the potentials within subjective quality rating and enhance the prediction performance and generalizability of the network. It is also shown RichIQA outperforms state-of-the-art competitors on multiple large-scale in the wild IQA databases with rich subjective rating labels
Paper 3:
Y. Xue, B. Zhong, G. Jin, T. Shen, L. Tan, N. Li, "AVLTrack: Dynamic Sparse Learning for Aerial Vision-Language Tracking," in IEEE Transactions on Circuits and Systems for Video Technology, vol. 35, no. 8, pp. 7554-7567, Aug. 2025, doi: 10.1109/TCSVT.2025.3549953.
This work presents a flexible framework for aerial vision-language tracking called AVLTrack. It consists of three key components, a dynamic sparse learning (DSL) module, an efficient Transformer backbone, and a multi-level language perception (MLP) strategy. First, DSL sparsely connects language and images via dynamic sparse attention, providing accurate multi-modal prompts. To adapt to target state variations, the sparsity in DSL is dynamically adjusted based on semantic information, flexibly highlighting target-specific tokens. Next, the Transformer backbone follows highly parallelized one-stream architectures, allowing efficient multi-modal feature extraction and interaction. Finally, MLP enables the iterative interaction of language and visual information, aiming to utilize language priori to guide the generation of discriminative visual features. As an additional contribution of this work, the DTB70-NLP dataset is collected to facilitate UAV vision-language tracking. Experiments on WebUAV-3M and DTB70-NLP demonstrate the effective performance of AVLTrack compared to existing trackers, while maintaining a high running speed of 80.5 FPS. The dataset and codes are available at https://github.com/xyl-507/AVLTrack
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Paper 1:
Das, S., Riedel, S., Naeim, M., Brunion, M., Bertuletti, M., Benini, L., Ryckaert, J., Myers, J., Biswas, D. and Milojevic, D., 2024. "Bandwidth-Latency-Thermal Co-Optimization of Interconnect-Dominated Many-Core 3D-IC," IEEE Transactions on Very Large Scale Integration (VLSI) Systems. vol. 33, no. 2, pp. 346-357, Feb. 2025, doi: 10.1109/TVLSI.2024.3467148 https://ieeexplore.ieee.org/document/10720515
Summary: The article addresses the challenges faced by contemporary system-on-chips (SoCs) due to the increasing demands for memory bandwidth, capacity, and thermal stability, particularly in the context of advancing artificial intelligence (AI). It proposes architectural modifications for a many-core SoC designed to enhance on-chip cache memory bandwidth and optimize access latency. The SoC is fabricated using A10 nanosheet technology in a 3-D configuration, with thermal analyses conducted. Workload simulations demonstrate significant performance improvements, achieving up to 12-fold acceleration for a 64-core version and 2.5-fold for a 16-core version, accompanied by a 40% increase in die area and a 60% rise in power dissipation when using a 2-D design. In comparison, the 3-D design not only minimizes the physical footprint but also saves 20% in power consumption due to a 40% reduction in wirelength. The study emphasizes the importance of restructuring pipelines to optimize the benefits of 3-D technology for enhanced memory access and lower latency. Additionally, it explores thermal impacts of different 3-D partitioning approaches in high-performance computing (HPC) and mobile applications, finding that 3-D designs in mobile contexts only slightly increase maximum temperature (by about 2-3 °C) compared to 2-D, while HPC scenarios require careful partitioning strategies to effectively manage thermal constraints.
Paper 2:
G. Murali, M. Gyu Park and S. Kyu Lim, "3DNN-Xplorer: A Machine Learning Framework for Design Space Exploration of Heterogeneous 3-D DNN Accelerators," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 33, no. 2, pp. 358-370, Feb. 2025, doi: 10.1109/TVLSI.2024.3471496. https://ieeexplore.ieee.org/document/10715720
Summary: This paper introduces 3DNN-Xplorer, a novel machine learning (ML)-based framework for predicting the performance of heterogeneous 3-D deep neural network (DNN) accelerators. This framework enables design space exploration (DSE) of these accelerators with a two-tier compute-on-memory (CoM) configuration, considering 3-D physical design factors. The framework explores four distinct heterogeneous 3-D integration styles combining 28-nm and 16-nm technology nodes for both compute and memory tiers. Through extrapolation techniques and ML models trained on various accelerator configurations, the performance of larger systems is estimated, achieving a maximum absolute error of 13.9%. The framework considers area imbalance arising from different technology nodes by assuming equal numbers of PEs or on-chip memory capacity across integration styles. The analysis reveals that the heterogeneous 3-D style with 28-nm compute and 16-nm memory demonstrates energy-efficient performance, offering up to 50% energy savings and an 8.8% reduction in runtime compared to other 3-D integration styles. Conversely, the heterogeneous 3-D style with 16-nm compute and 28-nm memory proves area-efficient, exhibiting up to 8.3% runtime reduction compared to other 3-D styles.
Paper 3:
A. Almeida da Silva, L. Nogueira, A. Coelho, J. A. N. Silveira and C. Marcon, "Securet3d: An Adaptive, Secure, and Fault-Tolerant Aware Routing Algorithm for Vertically–Partially Connected 3D-NoC," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 33, no. 1, pp. 275-287, Jan. 2025, doi: 10.1109/TVLSI.2024.3500575 https://ieeexplore.ieee.org/document/10766899
Summary: This article presents Securet3d, a novel routing algorithm designed for multiprocessor systems-on-chip (MPSoCs) that utilize 3-D networks-on-chip (3D-NoCs), aimed at enhancing secure and fault-tolerant operations. As MPSoCs play a crucial role in achieving effective parallel computing by sharing resources across complex applications, implementing adaptive mechanisms to safeguard sensitive data is essential. Securet3d builds upon the existing Reflect3d algorithm, introducing a comprehensive mapping scheme for secure data pathways and improving the system’s fault tolerance. The algorithm's effectiveness is validated through comparisons with three other fault-tolerant routing algorithms in vertically-partially connected 3D-NoCs. All algorithms were developed in SystemVerilog and evaluated via simulations using ModelSim, and hardware synthesis was performed with Cadence’s Genus tool. The experimental results indicate that Securet3d not only reduces latency but also enhances cost-effectiveness compared to other methods. Implemented with a 28-nm technology library, Securet3d exhibits minimal area and energy overhead, demonstrating its scalability and efficiency. Moreover, during denial-of-service (DoS) attacks, Securet3d maintains relatively stable average packet latencies of 70, 90, and 29 clock cycles for uniform random, bit-complement, and shuffle traffic, respectively, which are significantly lower than the latencies observed in other algorithms lacking security mechanisms (5763, 4632, and 3712 clock cycles on average). These findings underscore Securet3d's superior security, scalability, and adaptability for complex communication systems.
IEEE Journal on Emerging and Selected Topics in Circuits and Systems
Paper 1:
Y. Sun et al., "GenPolar: Generative AI-Aided Complexity Reduction for Polar SCL Decoding," in IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 15, no. 2, pp. 312-324, June 2025, doi: 10.1109/JETCAS.2025.3561330.
[It's open access!]
Summary: As 6G technologies advance, the high complexity of successive cancellation list (SCL) decoding for polar codes becomes a critical hurdle, while existing complexity reduction strategies suffer from limitations; generative AI (GenAI) technologies like Transformer models offer new potential to address these issues by modeling complex relationships in encoding and decoding processes. This paper proposes GenPolar, a hardware-friendly and GenAI-aided approach involving two-step optimization: Transformer encoders for generating polar construction sequences and a sorting entropy-based method for reducing unnecessary sorting operations. For polar codes of length-1024 with code rates of 0.25, 0.50, and 0.75, GenPolar achieves latency reductions of 20.6%, 29.8%, and 40.6% respectively, with negligible performance loss, and outperforms the reduced-complexity version of Fast-SCL decoding by 14.0%, 17.8%, and 22.3%
Paper 2:
G. Zhang, D. Zou, K. Sun, Z. Chen, M. Wang and Z. Wang, "GEMMV: An LLM-Based Automated Performance-Aware Framework for GEMM Verilog Generation," in IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 15, no. 2, pp. 325-336, June 2025, doi: 10.1109/JETCAS.2025.3568712.
Summary: As a major performance and energy bottleneck in AI accelerators, General Matrix Multiplication (GEMM) design is time-consuming and expertise-intensive, making LLMs highly promising for automating GEMM hardware design. However, lack of specialized hardware datasets and the absence of performance awareness in LLMs render existing LLM-based RTL generation methods inadequate for GEMM hardware design. This study proposes GEMMV, a performance-aware LLM-based framework that automatically generates optimized GEMM hardware designs. It introduces the first automated approach for creating a well-annotated Verilog dataset across GEMM variants and integrates performance models spanning from the microarchitecture to the system level into fine-tuned LLMs to enable performance awareness. Compared to prior work, GEMMV improves syntax correctness by 65% and functional correctness by 70%, while the GEMM modules generated by GEMMV achieve a 3.1× reduction in latency.
Paper 3:
J. Ryu and H. -J. Yoo, "An Overview of Neural Rendering Accelerators: Challenges, Trends, and Future Directions," in IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 15, no. 2, pp. 299-311, June 2025, doi: 10.1109/JETCAS.2025.3561777. [It's open access!]
Summary: Rapid advancements in neural rendering have revolutionized the fields of augmented reality (AR) and virtual reality (VR) by enabling photorealistic 3D modeling and rendering. However, deploying neural rendering on edge devices presents significant challenges due to computational complexity, memory inefficiencies, and energy constraints. This paper provides a comprehensive overview of neural rendering accelerators, identifying the major hardware inefficiencies across sampling, positional encoding, and multi-layer perception (MLP) stages. We explore hardware-software co-optimization techniques that address these challenges and provide a summary for in-depth analysis. Additionally, emerging trends like 3D Gaussian Splatting (3DGS) and hybrid rendering approaches are briefly introduced, highlighting their potential to improve rendering quality and efficiency. By presenting a unified analysis of challenges, solutions, and future directions, this work aims to guide the development of next-generation neural rendering accelerators, especially for resource-constrained environments
IEEE Open Journal of Circuits and Systems
Paper 1:
T. Kaiser, E. Gottschalk, K. Biethahn and F. Gerfers, "Pasithea-1: An Energy-Efficient Sequential Reconfigurable Array With CPU-Like Programmability," IEEE Open Journal of Circuits and Systems, vol. 6, pp. 1-13, 2025, doi: 10.1109/OJCAS.2024.3518110. https://ieeexplore.ieee.org/document/10802954
Summary: This work presents Pasithea-1, a coarse-grained reconfigurable array (CGRA) that combines energy efficiency with CPU-like programmability.
Paper 2:
B. Yang, T. Caldwell and A. Chan Carusone, "An Energy-Efficient Pipeline-SAR ADC Using Linearized Dynamic Amplifiers and Input Buffer in 22nm FDSOI," IEEE Open Journal of Circuits and Systems, vol. 6, pp. 50-62, 2025, doi: 10.1109/OJCAS.2024.3509746. https://ieeexplore.ieee.org/document/10774063
Summary: This work presents a dynamic amplifier that achieves −52 dB in total harmonic distortion through an analog technique by which the expanding and compressing nonlinearities in the input transistors cancel one another. A pipeline-SAR analog-to-digital converter incorporating the linearized dynamic amplifier in both the input buffer and the first residue amplifier stage was designed and fabricated using the GlobalFoundries 22nm fully depleted silicon-on-insulator process.
Paper 3:
S. Nowshin Chowdhury, M. Chen and S. Shah, "Analysis and Verilog-A Modeling of Floating-Gate Transistors," IEEE Open Journal of Circuits and Systems, vol. 6, pp. 63-73, 2025, doi: 10.1109/OJCAS.2024.3524363. https://ieeexplore.ieee.org/document/10818976
Summary: This work presents a Verilog-A model based on empirical measurements for a floating-gate transistor fabricated using a 65 nm CMOS process.
________________
IEEE CAS Magazine Second Quarter Issue 2025
Now available: Second Quarter Issue
IEEE Circuits and Systems (CAS) Magazine publishes original review articles and other articles that are of broad interest to the Circuits and Systems Society community. Interested authors are invited to send a three to four page White Paper first to the Editor-in-Chief, Prof. Keshab K. Parhi, by email here. If invited, they can submit a Full Paper at the Author Portal at the link below. CAS Magazine will continue to publish articles related to CAS Society Outreach. In addition, CAS Magazine also publishes articles related to education (such as tricks in solving problems and short lecture notes), conference highlights, chapter highlights, applications, and standards. Please feel free to submit articles that are of broad interest to the members of the CAS Society. For more information, please visit the IEEE Circuits and Systems Magazine on the CASS website.
________________
Active "Call for Papers” Archive
______________________________
Latest Tables of Contents of CAS Sponsored Journals
The latest issues of our CAS sponored journals have been published and the tables of contents can be accessed through the following links:
- IEEE Transactions on Circuits and Systems I: Regular Papers
- IEEE Transactions on Circuits and Systems II: Express Briefs
- IEEE Transactions on Circuits and Systems for Video Technology
- IEEE Journal on Emerging and Selected Topics in Circuits and Systems
- IEEE Circuits and Systems Magazine
- IEEE Transactions on Biomedical Circuits and Systems
- IEEE Design and Test Magaz