IEEE Circuits and Systems Society Newsletter | Volume 18 | Issue 4 | August 2024 | CURRENT/PAST ISSUES

PUBLICATION NEWS


Our Editors-in-Chief’s Top Picks

The Editors-in-Chief of our CASS publications have selected some noteworthy papers from the recent issues of our journals:


IEEE Transactions on Circuits and Systems I: Regular Papers

Paper 1:

Y. Ren, H. Harb, Y. Shen, A. Balatsoukas-Stimming and A. Burg, "A Generalized Adjusted Min-Sum Decoder for 5G LDPC Codes: Algorithm and Implementation," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 71, no. 6, pp. 2911-2924, June 2024, doi: 10.1109/TCSI.2024.3368056. https://ieeexplore.ieee.org/document/10461640

Summary: 5G New Radio (NR) has stringent demands on both performance and complexity for the design of LDPC decoding algorithms and corresponding decoder implementations as integrated circuits. Furthermore, decoders must fully support the wide range of all 5G NR block lengths and code rates, which is a significant challenge.

In this paper, we present a high-performance and low-complexity LDPC decoder, tailor-made to fulfill all 5G requirements. The proposed generalized adjusted min-sum (GA-MS) decoding in hardware-friendly fixed-point arithmetic has only a 0.1dB gap compared to floating-point belief propagation decoding. Moreover, we present a reconfigurable LDPC decoder implementation, compatible with all 5G NR LDPC codes. The corresponding 28nm FD-SOI ASIC design achieves a peak throughput of 24.42 Gbps and a maximum area efficiency of 13.40 Gbps/mm^2 at 4 decoding iterations, which provides a good solution for high-performance 5G modems.


Paper 2:

A. Batabyal, R. H. Zele, S. K. Khyalia and H. Wang, "A 0.065 mm² Inductive Coupling Based Dual Core mm-Wave VCO With 183 dBc/Hz FoMT," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 71, no. 6, pp. 2550-2562, June 2024, doi: 10.1109/TCSI.2024.3359294. 
https://ieeexplore.ieee.org/document/10431552

Summary: Next generation wireless communication networks drive the need for mm-Wave frequency bands. Generation of on-chip mm-Wave signals having high spectral purity across a broad bandwidth is challenging. Coupling of multiple VCO cores reduces phase noise. Resonant mode switching between multiple cores has been viewed as a solution to obtain an increase in tuning range.

This paper presents a novel dual-core inductive coupling-based area-efficient mm-Wave voltage-controlled oscillator fabricated in 40 nm CMOS process for K-band applications. New inductive coupling techniques have been implemented for mode switching between two VCO cores. Experimental results demonstrate low phase noise over a wide tuning range.


Paper 3:

Y. Gao, W. Ma, D. Lu, B. Zhu, P. Jia and M. Yu, "A Coupling Matrix Synthesized Three-Dimensional Filtering Power Amplifier," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 71, no. 7, pp. 3074-3085, July 2024, doi: 10.1109/TCSI.2024.3352603. 
https://ieeexplore.ieee.org/document/10459252

Summary: Is the concept of the “circuits” limited to the lumped elements, such as capacitors, inductors or resistors? The answer is no. In 3D electric components, the circuits may be realized by the EM dispersion properties of the waveguide, electric/magnetic field distribution, or EM couplings.

The 3D electric components are widely used in high-frequency and high-power systems, such as base-stations, radars, and satellites. Herein, the coupling matrix is developed for designing the 3D filtering power amplifier. The conventional planar matching circuits of the amplifier can be removed, allowing for reduced losses, improved efficiency, and compact architecture.


Paper 4:

E. Shaulov, T. Elazar and E. Socher, "A High Sensitivity CMOS Rectifier for 5G mm-Wave Energy Harvesting," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 71, no. 7, pp. 3041-3049, July 2024, doi: 10.1109/TCSI.2024.3368000. 
https://ieeexplore.ieee.org/document/10449887

Summary: Harvesting RF cellular power has vast potential to reduce battery reliance in low-power, wireless electronics. However, the challenge of efficiently converting the low-power RF signal to dc power remains a challenge, especially in the mm-Wave domain and, even more so, for CMOS.

This work proposes a power-splitting and voltage-summation rectifier design technique that allows one to target a specific output voltage while optimizing power conversion efficiency (PCE). By splitting the input power to n rectifiers and series connecting them in dc, PCE saturation is mitigated and high output voltage can be achieved. This technique is thoroughly investigated in simulation and modelling, and validated by fabrication (TSMC 65 nm) and measurements where the proposed design achieves a record 400 mV output voltage and 15% PCE for -10 dBm input power at 28 GHz.


IEEE Transactions on Circuits and Systems II: Express Briefs

Paper 1:

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P. Yang, F. Li and Z. Wang, "A 14-Bit 4 GS/s Two-Way Interleaved Pipelined ADC With Aperture Error Tunning," IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 71, no. 6, pp. 2961-2965, June 2024, doi: 10.1109/TCSII.2024.3355739.  https://ieeexplore.ieee.org/document/10404053

Summary: This paper reports a 14-bit 4 GS/s time-interleaving ADC design using two interleaved sub-ADCs in 28 nm CMOS technology and uses pipelined structure to have a high resolution at the same time. The ADC achieves 59.7 dB SNDR, 60.3 dB SNR and 69.3 dBc SFDR at 1.95 GHz input frequency. The ADC power consumption is 782 mW, resulting in 247.8 fJ/conv.-step FoMW and 153.7 dB FoMS.


Paper 2:

Y. Oh et al., "A 100-Gb/s PAM-8 Transmitter With 3-Tap FFE and High-Swing Hybrid Driver in 40-nm CMOS Technology," IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 71, no. 6, pp. 2936-2940, June 2024, doi: 10.1109/TCSII.2024.3354112.  https://ieeexplore.ieee.org/document/10399952

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Summary: This work presented a 100-Gb/s eight-level pulse amplitude modulation (PAM-8) transmitter (TX) for next-generation wireline communication systems. The transmitter employs a reconfigurable 3-tap FFE for adaptive channel equalization. The transmitter is fabricated in a 40-nm CMOS technology, with worst-case eye-opening values of 52 mV with FFE and 1.5-V peak-to-peak differential (Vppd) output swing without FFE, and the measured energy efficiency is 4.42 pJ/bit.


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Paper 3:

K. Xiao et al., "A 28nm 8Kb Reconfigurable SRAM Computing-In-Memory Macro With Input-Sparsity Optimized DTC for Multi-Mode MAC Operations," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 71, no. 7, pp. 3263-3267, July 2024, doi: 10.1109/TCSII.2024.3360284 https://ieeexplore.ieee.org/document/10416891

Summary: In this brief, a reconfigurable SRAM CIM macro supporting multi-mode multiply-and-accumulate (MAC) operations, including binary weight network (BWN) MAC, ternary weight network (TWN) MAC, and multi-bit MAC operations, is presented. The 8Kb macro is verified in a 28 nm CMOS with an energy efficiency of 1773.5 TOPS/W in BWN mode, achieving an accuracy of 84.35% on the CIFAR-10 dataset at 4b precision in inputs and weights.


IEEE Journal on Emerging and Selected Topics in Circuits and Systems

Paper 1:

H. Sun, Q. Yi and M. Fujita, "FPGA Codec System of Learned Image Compression With Algorithm-Architecture Co-Optimization," IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 14, no. 2, pp. 334-347, June 2024, doi: 10.1109/JETCAS.2024.3386328. https://ieeexplore.ieee.org/document/10494759

FPGA CODEC

Summary: FPGA architecture accelerates the coding time of learned image compression (LIC), however, the separate manner of algorithm and architecture development can easily cause a layout problem such as routing congestion when the hardware utilization is high. This paper gives an algorithm-architecture co-optimization of LIC by 1) restricting the input and output channel parallelism to increase the DSP usage and 2) adjusting the number of channels to increase the DSP efficiency. Compared with one recent work with a fine-grained pipelined architecture, we can reach up to 1.5x faster throughput with almost the same coding performance on the Kodak dataset.

Paper 2:

P. Du, Y. Liu and N. Ling, "CGVC-T: Contextual Generative Video Compression With Transformers," IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 14, no. 2, pp. 209-223, June 2024, doi: 10.1109/JETCAS.2024.3387301. https://ieeexplore.ieee.org/document/10496072

CGVC-T

Summary: The motivation of this work is to improve the perceptual quality of compressed videos at low bit rates, so that it is beneficial in low bandwidth scenarios and in applications that require reconstructing video texture details. To achieve this goal, for the first time in the literature, we propose contextual coding and hybrid transformer-convolution structure in a generative adversarial network-based video compression framework, along with novel transformer-based entropy models. The experiments on HEVC, UVG, and MCL-JCV datasets demonstrate that the perceptual quality of our video compression method in terms of FID, KID, and LPIPS scores surpasses state-of-the-art learned video codecs, the industrial video codecs x264 and x265, as well as the official reference software JM, HM, and VTM.

Paper 3:

Y. Zeng et al., "Physically Guided Generative Adversarial Network for Holographic 3D Content Generation From Multi-View Light Field," IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 14, no. 2, pp. 286-298, June 2024, doi: 10.1109/JETCAS.2024.3386672. https://ieeexplore.ieee.org/document/10495040

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Summary: Achieving high-fidelity three-dimensional (3D) scene representation through holography is challenging due to the unknown mechanisms of optimal hologram generation, significant computational load and memory usage, and the limitations of existing methods that predominantly focus on optimizing the central viewpoint while neglecting the fidelity of holographic reconstructions across a wide angular range. We propose a Physically Guided Generative Adversarial Network (PGGAN), the first generative model designed to directly transform multi-view light fields into holographic 3D content. PGGAN uniquely integrates the fidelity of data-driven learning with the rigor of physical optics principles, ensuring consistent reconstruction quality across a wide field of view. PGGAN generates detailed holograms in as little as 0.002 seconds, significantly outperforming current state-of-the-art techniques in speed while maintaining superior angular reconstruction fidelity.


IEEE Transactions on Circuits and Systems for Video Technology

Paper 1

Q. Cheng, Z. Tan, K. Wen, C. Chen and X. Gu, "Semantic Pre-Alignment and Ranking Learning With Unified Framework for Cross-Modal Retrieval," IEEE Transactions on Circuits and Systems for Video Technology, vol. 34, no. 7, pp. 6503-6516, July 2024, doi: 10.1109/TCSVT.2022.3182549 https://ieeexplore.ieee.org/document/9794649

Summary: This paper proposes a Unified framework with Ranking Learning (URL) for cross-modal retrieval. The unified framework consists of three sub-networks: a visual network, a textual network, and an interaction network. The visual network and the textual network project the image and text features into their corresponding hidden spaces; the interaction network forces the target image-text representation to align in the common space. For unifying both semantics and rankings, a new optimization paradigm is proposed that includes pre-alignment for semantic knowledge transfer and ranking learning for final retrieval. The former focuses on the semantic pre-alignment optimized by semantic classification and the latter revolves around the retrieval rankings. For the ranking learning, a cross-AP loss is introduced that can directly optimize the retrieval metric average precision for cross-modal retrieval. Experiments on the Wikipedia, Pascal Sentence, NUS-WIDE-10k, and PKU XMediaNet datasets show high retrieval precision.

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Figure (right): (a) A general person re-identification method based on 2D images; (b) The method proposed in this paper to learn pedestrian features from a 3D space.





The proposed architecture consists of two paths: the visual path and the textual path. The visual path contains a VGG19 image encoder, a visual network and a weight-sharing cross-interaction network. The textual path has a text encoder, textual network and the same weight-sharing cross-interaction network. Three objectives are designed to supervise the visual and textual representation learning.


Paper 2:

J. Wang, F. Li, Y. An, X. Zhang and H. Sun, "Toward Robust LiDAR-Camera Fusion in BEV Space via Mutual Deformable Attention and Temporal Aggregation," in IEEE Transactions on Circuits and Systems for Video Technology, vol. 34, no. 7, pp. 5753-5764, July 2024, doi: 10.1109/TCSVT.2024.3366664. https://ieeexplore.ieee.org/document/10438483

Summary: LiDAR and camera are two sensors that provide complementary information for accurate 3D object detection. This paper analyzes the shortcomings of most fusion detectors, which rely mainly on the LiDAR branch, and the potential of the bird’s eye-view (BEV) paradigm in dealing with partial sensor failures. Based on that, a LiDAR-camera fusion pipeline in unified BEV space is presented with two novel designs under four typical LiDAR-camera malfunction cases. In particular, a mutual deformable attention is proposed to dynamically model the spatial feature relationship and reduce the interference caused by the corrupted modality, and a temporal aggregation module is devised to fully utilize the information in the temporal domain. Together with the decoupled feature extraction for each modality and holistic BEV space fusion, the detector proposed in this paper can work stably regardless of single-modality data corruption. Experiments on the nuScenes dataset under robust settings demonstrate the effectiveness of the approach

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The overall architecture of the method.


Paper 3:

Z. Yu, L. Li, J. Xie, C. Wang, W. Li and X. Ning, "Pedestrian 3D Shape Understanding for Person Re-Identification via Multi-View Learning," IEEE Transactions on Circuits and Systems for Video Technology, vol. 34, no. 7, pp. 5589-5602, July 2024, doi: 10.1109/TCSVT.2024.3358850.
https://ieeexplore.ieee.org/document/10415089

Summary: This paper proposes a network based on 3D multi-view learning, allowing it to acquire geometric and shape details of an occluded pedsestrian from 3D space. Simultaneously, it capitalizes on advancements in 2D-based networks to extract semantic representations from 3D multi-views. Specifically, the surface random selection strategy is proposed to convert images of 2D RGB into 3D multi-views. Using this strategy, four extensive 3D multi-view data collections are built for person ReID. After that, Pedestrian 3D Shape Understanding for Person Re-Identification via Multi-View Learning, called MV-3DSReID, is proposed for identifying the person by learning person geometry and structure representation from the groups of multi-view images. In comparison to alternative data formats like 2D RGB, or 3D point cloud, multi-view images complement each other’s detailed features of the 3D object by adjusting rendering viewpoints, thus facilitating a more comprehensive understanding of the person for both holistic and occluded ReID situations. Experiments on occluded and holistic ReID tasks demonstrate performance levels comparable to state-of-the-art methods, validating the effectiveness of the proposed approach in tackling challenges related to occlusion.

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The design of the MV-3DSReID backbone proposed in this paper. It incorporates a network structure where a pedestrian image is transformed into multi-view images through 3D reconstruction and rendering. Subsequently, a multi-view descriptor and a 2D descriptor are utilized to extract 3D multi-view features and 2D texture features. Following this, the 3D multi-view features and 2D texture features are combined into a unified space for predicting the persons’ ID. The model requires simultaneous input of both the multi-view and original images.


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IEEE CAS Magazine Latest Feature Articles: Special Issue on the 75th Anniversary of the IEEE CAS Society

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Past, Present, and Future of CASS Educational Programs and Initiatives

Fakhrul Zaman Rokhani, Xinmiao Zhang, Rajiv V. Joshi, Ricardo Reis, Victor Grimblatt, Kea-Tiong Tang, Yongfu Li, Amara Amara, and Manuel Delgado-Restituto

Superconductive Electronics: A 25-Year Review

Rassul Bairamkulov and Giovanni De Micheli

Cryogenic CMOS Design for Qubit Control: Present Status, Challenges, and Future Directions

Sudipto Chakraborty and Rajiv V. Joshi

PCI-Express: Evolution of a Ubiquitous Load-Store Interconnect Over Two Decades and the Path Forward for the Next Two Decades

Debendra Das Sharma

Fast Settling Phase-Locked Loops: A Comprehensive Survey of Applications and Techniques

Zeeshan Ali, Pallavi Paliwal, Meraj Ahmad, Hadi Heidari, and Shalabh Gupta

A Different View of Sigma-Delta Modulators Under the Lens of Pulse Frequency Modulation

Victor Medina, Pieter Rombouts, and Luis Hernandez-Corporales


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