Our Editors-in-Chief’s Top Picks
The Editors-in-Chief of our CASS publications have selected some noteworthy papers from the recent issues of our journals:
IEEE Transactions on Circuits and Systems II: Express Briefs
Paper 1:
H. An, H. Nam, S. Kim, Y. Lim and H. Yoon, "An Area-Efficient CMOS Cross-Coupled LC-VCO Using Nested Intertwined Tail Inductors," IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 72, no. 1, pp. 143-147, Jan. 2025, doi: 10.1109/TCSII.2024.3485921. https://ieeexplore.ieee.org/document/10734350
Summary: An area-efficient CMOS cross-coupled LC-VCO, operating from 5.74 GHz to 8.02 GHz and featuring a tail noise filter with two tail inductors integrated inside the main inductor, is introduced. The tail noise filter comprised two nested intertwined tail inductors (NITIs) and a tail capacitor bank, effectively suppressing phase noise (PN) while generating negligible magnetic couplings between the main inductor and the NITIs. Implemented in 28-nm CMOS process, it consumed 11 mA current from 0.73 V power supply. The LC-VCO achieved PN of −116.38 dBc/Hz at 1 MHz offset frequency for an output frequency of 5.747 GHz.
Paper 2:
C. Moon, I. Jang, S. Lim, Y. Huh and B. Kim, "3×16 Gb/s Compact Single-Ended PAM4 Transmitters With Inverter-Based Crosstalk Compensation for Memory Interfaces," IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 71, no. 12, pp. 4884-4888, Dec. 2024, doi: 10.1109/TCSII.2024.3440999. https://ieeexplore.ieee.org/document/10632065
Summary: A four-level pulse-amplitude modulation (PAM4) transmitter (TX) with crosstalk compensation (XTC) is proposed for short-reach memory interfaces. Simple encoders and transition detectors detect the data pattern causing crosstalk and appropriately activate inverter-based XTC taps. With gain and delay control of XTC, compensation error due to the mismatch between the victim and aggressor channels was minimized. The TX was fabricated in 28 nm LP CMOS and tested at 16 Gb/s. With XTC, the eye height and width were improved by 203% and 396%, respectively. Because it uses area-efficient inverter-based XTC taps, the TX occupies only 0.0067 mm2, achieving an area per data rate of 0.00042 mm2/Gbps.
Paper 3:
J. Maeng, I. Park, J. Jeon, H. Kim, H. Lee and C. Kim, "A Tri-Mode Reconfigurable DC-DC Converter With Photovoltaic Energy Harvesting for Miniature IoT Batteries," IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 71, no. 12, pp. 4844-4848, Dec. 2024, doi: 10.1109/TCSII.2024.3437449 https://ieeexplore.ieee.org/document/10621596
Summary: This brief proposes a reconfigurable DC-DC converter for an energy-harvesting system with a tri-mode recharging method for miniature Internet of Things (IoT) batteries operating at various temperatures. The proposed system and IoT battery operate at temperatures as low as –5C with an internal resistance of up to 1.9 k Ω . The proposed recharging method utilizes a low-dropout regulator and DC-DC converter with a negative inductor current to rapidly recharge a storage capacitor and isolate the IoT battery from the it. With a 180 nm CMOS process, the charge of the capacitor can be restored rapidly with the aid of the IoT battery, which reduces the ratio of the activation time to the recharging time to 0.27 at –5C.
IEEE Transactions on Circuits and Systems for Video Technologies
Paper 1:
X. He, M. Qiao, P. Li, P. Chang, T. Zhang, X. Guo, J. Wang, Z. Tian, and G. Zhou, "Multi-View Graph Convolutional Network With Spectral Component Decompose for Remote Sensing Images Classification," IEEE Transactions on Circuits and Systems for Video Technology, vol. 35, no. 1, pp. 3-18, Jan. 2025, doi: 10.1109/TCSVT.2022.3227172 https://ieeexplore.ieee.org/document/9970571
Summary: This paper proposes a multi-view Graph Convolutional Network (GCN)-based representation learning network (MvRLNet) for Remote Sensing image classification. First, a superpixel-based spectral component decomposes module (SSCDM) is designed to enhance the uniqueness and homogeneity of graph nodes because the mixed superpixels may lead to miscellaneous information on graph aggregations. Second, a multi-view graph learning module (MGLM) is proposed to integrate topology and spectral graph information into a unified network with an effective feature learning strategy. The effectiveness of the method proposed in this paper, MvRLNet, is validated on a variety of datasets with different resolutions. The experimental results show that the proposed MvRLNet performs comparably or better than state-of-the-art techniques.
Paper 2:
M. Ju, C. He, C. Ding, W. Ren, L. Zhang and K. -K. Ma, "All-Inclusive Image Enhancement for Degraded Images Exhibiting Low-Frequency Corruption," IEEE Transactions on Circuits and Systems for Video Technology, vol. 35, no. 1, pp. 838-856, Jan. 2025, doi: 10.1109/TCSVT.2024.3465875 https://ieeexplore.ieee.org/document/10685536
Summary: This paper proposes an image enhancement method, called the all-inclusive image enhancement (AIIE) that can enhance the degraded images for improving the visibility of image content. These imageries were acquired under various types of weather conditions such as haze, low-light, underwater, sandstorm, etc. One commonality shared by this class of noise is that the resulted degradations on visual quality or visibility are caused by low-frequency interference. Existing image enhancement methods lack the ability to deal with all types of degradations from this class, while the method proposed in this paper, AIIE, offers a unified treatment for them. To achieve this goal, a statistical property is obtained from the study of the discrete cosine transform (DCT) of 1,000 high- and 1000 low-quality images on their DCT domains. It shows that the normalized DCT coefficients (between 0 and 1) of high-quality images has about 95% fall in the interval [0, 0.2]; for low-quality images, almost all the coefficients are in the same interval. This property, called the DCT prior (DCT-P), is instrumental to the development of the AIIE algorithm proposed in this paper. Since the proposed DCT-P delineates the attributes of high- and low-quality images clearly, it becomes a ‘tool’ to convert low-quality images to their enhanced version. Extensive experimental results show the performance of the AIIE conducted on different types of deteriorated images in terms of visual quality and efficiency. Results also show significant advantages on computational complexity, which is essential for real-time applications.
Paper 3:
Y. Pan, R. Sun, Y. Wang, W. Yang, T. Zhang and Y. Zhang, "Purify Then Guide: A Bi-Directional Bridge Network for Open-Vocabulary Semantic Segmentation," IEEE Transactions on Circuits and Systems for Video Technology, vol. 35, no. 1, pp. 343-356, Jan. 2025, doi: 10.1109/TCSVT.2024.3464631 https://ieeexplore.ieee.org/document/10684834
Summary: This paper proposes a bi-directional bridge network (BBN) to bridge the gap between upstream pre-trained models and downstream segmentation tasks. It first purifies the noisy text embedding and then guides semantics-vision aggregation with the purified information in a purification-then-guidance manner, thereby facilitating effective semantic utilization. Specifically, an optimal purification modulator is designed to purify noisy text information via the optimal transport algorithm, and a reliable guidance modulator to integrate proper textual information into vision embedding via the designed reliable attention in an adaptive manner. Extensive experimental results on five challenging benchmarks demonstrate that BBN performs favorably against state-of-the-art open-vocabulary semantic segmentation methods.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Paper 1:
Das, S., Riedel, S., Naeim, M., Brunion, M., Bertuletti, M., Benini, L., Ryckaert, J., Myers, J., Biswas, D. and Milojevic, D., 2024. "Bandwidth-Latency-Thermal Co-Optimization of Interconnect-Dominated Many-Core 3D-IC," IEEE Transactions on Very Large Scale Integration (VLSI) Systems. vol. 33, no. 2, pp. 346-357, Feb. 2025, doi: 10.1109/TVLSI.2024.3467148 https://ieeexplore.ieee.org/document/10720515
Summary: The article addresses the challenges faced by contemporary system-on-chips (SoCs) due to the increasing demands for memory bandwidth, capacity, and thermal stability, particularly in the context of advancing artificial intelligence (AI). It proposes architectural modifications for a many-core SoC designed to enhance on-chip cache memory bandwidth and optimize access latency. The SoC is fabricated using A10 nanosheet technology in a 3-D configuration, with thermal analyses conducted. Workload simulations demonstrate significant performance improvements, achieving up to 12-fold acceleration for a 64-core version and 2.5-fold for a 16-core version, accompanied by a 40% increase in die area and a 60% rise in power dissipation when using a 2-D design. In comparison, the 3-D design not only minimizes the physical footprint but also saves 20% in power consumption due to a 40% reduction in wirelength. The study emphasizes the importance of restructuring pipelines to optimize the benefits of 3-D technology for enhanced memory access and lower latency. Additionally, it explores thermal impacts of different 3-D partitioning approaches in high-performance computing (HPC) and mobile applications, finding that 3-D designs in mobile contexts only slightly increase maximum temperature (by about 2-3 °C) compared to 2-D, while HPC scenarios require careful partitioning strategies to effectively manage thermal constraints.
Paper 2:
G. Murali, M. Gyu Park and S. Kyu Lim, "3DNN-Xplorer: A Machine Learning Framework for Design Space Exploration of Heterogeneous 3-D DNN Accelerators," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 33, no. 2, pp. 358-370, Feb. 2025, doi: 10.1109/TVLSI.2024.3471496. https://ieeexplore.ieee.org/document/10715720
Summary: This paper introduces 3DNN-Xplorer, a novel machine learning (ML)-based framework for predicting the performance of heterogeneous 3-D deep neural network (DNN) accelerators. This framework enables design space exploration (DSE) of these accelerators with a two-tier compute-on-memory (CoM) configuration, considering 3-D physical design factors. The framework explores four distinct heterogeneous 3-D integration styles combining 28-nm and 16-nm technology nodes for both compute and memory tiers. Through extrapolation techniques and ML models trained on various accelerator configurations, the performance of larger systems is estimated, achieving a maximum absolute error of 13.9%. The framework considers area imbalance arising from different technology nodes by assuming equal numbers of PEs or on-chip memory capacity across integration styles. The analysis reveals that the heterogeneous 3-D style with 28-nm compute and 16-nm memory demonstrates energy-efficient performance, offering up to 50% energy savings and an 8.8% reduction in runtime compared to other 3-D integration styles. Conversely, the heterogeneous 3-D style with 16-nm compute and 28-nm memory proves area-efficient, exhibiting up to 8.3% runtime reduction compared to other 3-D styles.
Paper 3:
A. Almeida da Silva, L. Nogueira, A. Coelho, J. A. N. Silveira and C. Marcon, "Securet3d: An Adaptive, Secure, and Fault-Tolerant Aware Routing Algorithm for Vertically–Partially Connected 3D-NoC," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 33, no. 1, pp. 275-287, Jan. 2025, doi: 10.1109/TVLSI.2024.3500575 https://ieeexplore.ieee.org/document/10766899
Summary: This article presents Securet3d, a novel routing algorithm designed for multiprocessor systems-on-chip (MPSoCs) that utilize 3-D networks-on-chip (3D-NoCs), aimed at enhancing secure and fault-tolerant operations. As MPSoCs play a crucial role in achieving effective parallel computing by sharing resources across complex applications, implementing adaptive mechanisms to safeguard sensitive data is essential. Securet3d builds upon the existing Reflect3d algorithm, introducing a comprehensive mapping scheme for secure data pathways and improving the system’s fault tolerance. The algorithm's effectiveness is validated through comparisons with three other fault-tolerant routing algorithms in vertically-partially connected 3D-NoCs. All algorithms were developed in SystemVerilog and evaluated via simulations using ModelSim, and hardware synthesis was performed with Cadence’s Genus tool. The experimental results indicate that Securet3d not only reduces latency but also enhances cost-effectiveness compared to other methods. Implemented with a 28-nm technology library, Securet3d exhibits minimal area and energy overhead, demonstrating its scalability and efficiency. Moreover, during denial-of-service (DoS) attacks, Securet3d maintains relatively stable average packet latencies of 70, 90, and 29 clock cycles for uniform random, bit-complement, and shuffle traffic, respectively, which are significantly lower than the latencies observed in other algorithms lacking security mechanisms (5763, 4632, and 3712 clock cycles on average). These findings underscore Securet3d's superior security, scalability, and adaptability for complex communication systems.
IEEE Journal on Emerging and Selected Topics in Circuits and Systems
Paper 1:
Y. Zheng, C. -H. Chang, S. -H. Huang, P. -Y. Chen and S. Picek, "An Overview of Trustworthy AI: Advances in IP Protection, Privacy-Preserving Federated Learning, Security Verification, and GAI Safety Alignment," IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 14, no. 4, pp. 582-607, Dec. 2024, doi: 10.1109/JETCAS.2024.3477348. https://ieeexplore.ieee.org/document/10711270
Summary: This overview paper anchors on recent advances in four research hotspots of trustworthy AI with compelling and challenging security, privacy, and safety issues. The topics discussed include the intellectual property protection of deep learning and generative models, the trustworthiness of federated learning, verification and testing tools of AI systems, and the safety alignment of generative AI systems. Discussions regarding the challenges and opportunities associated with each topic are also presented, with the hope of inspiring potential research directions and steering technological advancement toward the development of beneficial AI.
Paper 2:
B. Belgodere et al., "Auditing and Generating Synthetic Data With Controllable Trust Trade-Offs," in IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 14, no. 4, pp. 773-788, Dec. 2024, doi: 10.1109/JETCAS.2024.3477976. https://ieeexplore.ieee.org/document/10713321
Summary: Synthetic datasets help tackle critical challenges like biases, imbalances, and privacy risks in real-world data, but ensuring their trustworthiness remains a significant hurdle. To address this, we propose a comprehensive auditing framework that evaluates generative AI models and synthetic datasets across tabular, time-series, vision, and natural language data for bias prevention, fidelity, privacy preservation, and utility. Our auditing framework provides clear, transparent reports via communicating trustworthiness indices, that ensure trust and compliance in synthetic data generation.
Paper 3:
S. Shukla, M. Alam, P. Mitra and D. Mukhopadhyay, "Stealing the Invisible: Unveiling Pre-Trained CNN Models Through Adversarial Examples and Timing Side-Channels," IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 14, no. 4, pp. 634-646, Dec. 2024, doi: 10.1109/JETCAS.2024.3485133. https://ieeexplore.ieee.org/document/10731906
Summary: Machine Learning as a Service (MLaaS) platforms increasingly rely on pre-trained models, making it vital to safeguard architectures and address their vulnerabilities. We introduce ArchWhisperer, a novel model fingerprinting attack that exploits adversarial image misclassifications and inference time profiling to efficiently steal CNN and Vision Transformer architectures. Our approach achieves 88.8% accuracy across 27 pre-trained models on CIFAR-10 while keeping the query budget below 20, significantly outperforming prior works.
IEEE Open Journal of Circuits and Systems
Paper 1:
T. Kaiser, E. Gottschalk, K. Biethahn and F. Gerfers, "Pasithea-1: An Energy-Efficient Sequential Reconfigurable Array With CPU-Like Programmability," IEEE Open Journal of Circuits and Systems, vol. 6, pp. 1-13, 2025, doi: 10.1109/OJCAS.2024.3518110. https://ieeexplore.ieee.org/document/10802954
Summary: This work presents Pasithea-1, a coarse-grained reconfigurable array (CGRA) that combines energy efficiency with CPU-like programmability.
Paper 2:
B. Yang, T. Caldwell and A. Chan Carusone, "An Energy-Efficient Pipeline-SAR ADC Using Linearized Dynamic Amplifiers and Input Buffer in 22nm FDSOI," IEEE Open Journal of Circuits and Systems, vol. 6, pp. 50-62, 2025, doi: 10.1109/OJCAS.2024.3509746. https://ieeexplore.ieee.org/document/10774063
Summary: This work presents a dynamic amplifier that achieves −52 dB in total harmonic distortion through an analog technique by which the expanding and compressing nonlinearities in the input transistors cancel one another. A pipeline-SAR analog-to-digital converter incorporating the linearized dynamic amplifier in both the input buffer and the first residue amplifier stage was designed and fabricated using the GlobalFoundries 22nm fully depleted silicon-on-insulator process.
Paper 3:
S. Nowshin Chowdhury, M. Chen and S. Shah, "Analysis and Verilog-A Modeling of Floating-Gate Transistors," IEEE Open Journal of Circuits and Systems, vol. 6, pp. 63-73, 2025, doi: 10.1109/OJCAS.2024.3524363. https://ieeexplore.ieee.org/document/10818976
Summary: This work presents a Verilog-A model based on empirical measurements for a floating-gate transistor fabricated using a 65 nm CMOS process.
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IEEE CAS Magazine First Quarter Issue 2025
IEEE Circuits and Systems (CAS) Magazine publishes original review articles and other articles that are of broad interest to the Circuits and Systems Society community. Interested authors are invited to send a three to four page White Paper first to the Editor-in-Chief, Prof. Keshab K. Parhi, by email here. If invited, they can submit a Full Paper at the Author Portal at the link below. CAS Magazine will continue to publish articles related to CAS Society Outreach. In addition, CAS Magazine also publishes articles related to education (such as tricks in solving problems and short lecture notes), conference highlights, chapter highlights, applications, and standards. Please feel free to submit articles that are of broad interest to the members of the CAS Society. For more information, please visit the IEEE Circuits and Systems Magazine on the CASS website.
Table of Contents
Beginning of a New Year and a New Quarter Century [Editorial]
Keshab K. Parhi
75th Anniversary of the IEEE CAS Society [President’s Message]
Myung Hoon Sunwoo
Secure Machine Learning Hardware: Challenges and Progress [Feature]
Kyungmi Lee; Maitreyi Ashok; Saurav Maji; Rashmi Agrawal; Ajay Joshi; Mengjia Yan; Joel S. Emer; Anantha P. Chandrakasan
A Survey: Collaborative Hardware and Software Design in the Era of Large Language Models
Cong Guo; Feng Cheng; Zhixu Du; James Kiessling; Jonathan Ku; Shiyu Li; Ziru Li; Mingyuan Ma; Tergel Molom-Ochir; Benjamin Morris; Haoxuan Shan; Jingwei Sun; Yitu Wang; Chiyue Wei; Xueying Wu; Yuhao Wu; Hao Frank Yang; Jingyang Zhang; Junyao Zhang; Qilin Zheng; Guanglei Zhou; Hai Li; Yiran Chen
Linearity Through Democracy [Feature]
Enrique Alvarez-Fontecilla; Paul S. Wilkins
Celebrating 15 Years of IEEE Latin American Symposium on Circuits and Systems (LASCAS) [CASS Regional Conference Celebration]
Francois Rivet; Carlos Silva-Cardenas; Fernando Silveira; Victor Grimblatt; Ricardo Reis
Creating a Sustainable Future Workshop: Cultivating a Green and Resilient Environment in CAS and Reliability for Security in Hardware [CASS Regional Outreach]
Yi Wang; Kea-Tiong Tang
Webinar for IEEE CASS YPCAS by Prof. Zhicong Huang [CASS Young Professionals Corner]
Chi-Seng Lam
IEEE Young Professionals in Circuits and Systems (YPCAS) Forum 2024 at University of Macau, Macau SAR, China [CASS Young Professionals Corner]
Chi-Seng Lam
IEEE Standards Workshop on AI for Healthcare [Standards Corner]
Yongfu Li; Jiajun Yuan; Yang Zhao; Liebin Zhao; Yong Lian
Empowering Open Innovation Through IEEE CAS Society Conferences’ Grand Challenges and the Development of Robust IEEE Standards [Open Innovations and Standards]
Yongfu Li; Yin Yong; Guoxing Wang; Liebin Zhao; Yong Lian
CASS Tainan Chapter Hosts Distinguished Lecturer Gabriel A. Rincon-Mora [CASS Chapter Highlights]
Cheng-Ta Chiang
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The TCASAI Inaugural Issue is Now Available!
We are thrilled to announce the inaugural issue of IEEE Transactions on Circuits and Systems for Artificial Intelligence (TCASAI) is now available.
TCASAI is co-sponsored by IEEE Circuits and Systems Society (IEEE CASS), IEEE Council on Electronic Design Automation (IEEE CEDA), IEEE Solid-State Circuits Society (IEEE SSCS) and technically co-sponsored by the IEEE Electron Devices Society (EDS) and the IEEE Nanotechnology Council.
As the first IEEE periodical dedicated to artificial intelligence (AI) hardware, the IEEE Transactions on Circuits and Systems for Artificial Intelligence (TCASAI) publishes contributions related to circuits and systems for artificial intelligence, including circuit and electronic system design, implementation, and demonstration.
The IEEE TCASAI is also thrilled to announce its inaugural editorial board, which can be viewed here.
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Active "Call for Papers” Archive
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Latest Tables of Contents of CAS Sponsored Journals
The latest issues of our CAS sponored journals have been published and the tables of contents can be accessed through the following links:
- IEEE Transactions on Circuits and Systems I: Regular Papers
- IEEE Transactions on Circuits and Systems II: Express Briefs
- IEEE Transactions on Circuits and Systems for Video Technology
- IEEE Journal on Emerging and Selected Topics in Circuits and Systems
- IEEE Circuits and Systems Magazine
- IEEE Transactions on Biomedical Circuits and Systems
- IEEE Design and Test Magaz